A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

Integrated circuit interconnect structures including an interconnect line metallization feature subjected to one or more chalcogenation techniques to form a cap may reduce line resistance. A top portion of a bulk line material may be advantageously crystallized into a metal chalcogenide cap with exceptionally large crystal structure. Accordingly, chalcogenation of a top portion of a bulk material can lower scattering resistance of an interconnect line relative to alternatives where the bulk material is capped with an alternative material, such as an amorphous dielectric or a fine grained metallic or graphitic material.

A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and conductive rails laterally adjacent to the conductive structures of the stack structure. The conductive rails comprise a material composition that is different than a material composition of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.

A semiconductor device includes active regions extending in a first direction on a substrate; a gate electrode intersecting the active regions on the substrate, extending in a second direction, and including a contact region protruding upwardly; and an interconnection line on the gate electrode and connected to the contact region, wherein the contact region includes a lower region having a first width in the second direction and an upper region located on the lower region and having a second width smaller than the first width in the second direction, and wherein at least one side surface of the contact region in the second direction has a point at which an inclination or a curvature is changed between the lower region and the upper region.

Disclosed embodiments include methods, apparatuses, integrated circuits, and circuit boards for power conversion with reduced parasitics. The apparatuses include an integrated circuit for power conversion. The integrated circuit includes a plurality of power transistors and a plurality of metal regions coupled to the power transistors. A first portion of the metal regions are coupled to source regions of the power transistors. A second portion of the metal regions are coupled to drain regions of the power transistors. The first and second portions have at least one of substantially equal numbers of metal regions, substantially equal resistances, or balanced distributions of metal regions.

The semiconductor stacked package including a semiconductor die. The semiconductor die includes a substrate, a transistor, and a through-silicon-via (TSV) structure. The transistor is over the substrate. The TSV structure penetrates the substrate and comprises a first conductive layer, a second conductive layer, and a dielectric layer. The dielectric layer is between the first conductive layer and the second conductive layer. The method of manufacturing the same includes the following steps: forming a via hole in a substrate; forming a first conductive layer in the via hole; forming a dielectric layer in the via hole and over the first conductive layer; forming a second conductive layer in the via hole and over the dielectric layer; and forming a transistor over the substrate. The first conductive layer, the dielectric layer, and the second conductive layer collectively form a through-silicon-via (TSV) structure.

A semiconductor package includes a laminate package body and a die assembly embedded within the laminate package body. The laminate package body includes a plurality of laminate dielectric layers stacked on top of one another and metallization layers interposed between the laminate dielectric layers. The die assembly includes a thermally conductive substrate that includes a planar upper surface, a semiconductor die mounted on the planar upper surface of the thermally conductive substrate, and an electrically insulating thickness-matching layer formed on the planar upper surface of the thermally conductive substrate and surrounding the semiconductor die. An upper surface of the electrically insulating thickness-matching layer is substantially coplanar with an upper surface of the semiconductor die. The upper surface of the electrically insulating thickness-matching layer and the upper surface of the semiconductor die form an upper surface of the die assembly.

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a transistor in the substrate. The transistor includes a gate structure penetrating through the substrate, a first source/drain region at a front side of the substrate, and a second source/drain region at a back side of the substrate.

A semiconductor device comprises a first transistor structure comprising a first gate region and a second gate region, a first dielectric layer disposed between the first gate region and the second gate region, a second transistor structure stacked on the first transistor structure and comprising a third gate region and a fourth gate region, and a second dielectric layer disposed between the third gate region and the fourth gate region. A conductive via is disposed through at least one of the first dielectric layer and the second dielectric layer, wherein at least one of the first gate region and the second gate region are electrically connected to at least one of the third gate region and the fourth gate region by the conductive via.