Scribe line channels are formed between semiconductor dies that are formed on a gallium nitride (GaN) layer using an aluminum nitride-based (AlN-based) core substrate. The scribe line channels are formed to expose a release layer under the GaN layer, which enables the release layer to be etched through the scribe line channels to remove the semiconductor dies from the AlN-based core substrate with minimal to no damage to the AlN-based core substrate. In this way, the scribe line channels enable the AlN-based core substrate to be reused for subsequent GaN layer growth, and increase the number of times that the AlN-based core substrate can be reused to form GaN-based semiconductor devices. This reduces the cost and complexity of manufacturing GaN-based semiconductor devices.

A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure includes: forming a sacrificial layer in a concave in a metal layer; recessing the sacrificial layer; filling a metal-organic framework layer in the concave; and removing the sacrificial layer to form an air gap in the concave.

A semiconductor structure including a substrate, a first transistor, and a first metal gate is provided. The substrate has a front side and a back side opposite to each other. The first transistor is located on the front side. The first transistor includes a first channel region. The first metal gate is located on the back side and aligned with the first channel region.

The present disclosure relates to methods, devices, systems, and techniques for managing semiconductor devices with stacked structures. An example semiconductor device includes a control semiconductor structure and array semiconductor structures. The array semiconductor structures are stacked along a first direction and are coupled to the control semiconductor structure. The array semiconductor structures include at least a first array semiconductor structure and a second array semiconductor structure. The first array semiconductor structure includes: a first array region; a first connection region adjacent to the first array region along a second direction perpendicular to the first direction; first bit line connection structures in the first array region; first word line contact structures extending along the first direction in the first connection region; and first word line connection structures extending along the first direction in the first connection region.

Embodiments of present invention provide a semiconductor structure. The structure includes a metal via having a substantially hyperboloid exterior shape; and a dielectric layer surrounding the metal via, where the metal via includes a bottom portion and a top portion; the top portion includes an outer liner and an inner liner at sidewalls thereof; and the bottom portion is directly surrounded by the dielectric layer. A method of forming the same is also provided.

Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions has a higher top than in the second regions. The seam tops in the second regions are elevationally-coincident with or below a bottom of an uppermost of the conductive tiers. Methods are disclosed.

A flash memory cell includes a channel structure, a first gate, a second gate, a storage structure, a source line pillar and a bit line pillar. The channel structure is formed over a substrate. The first gate is formed adjacent to the channel structure. The second gate is separated from the first gate and the channel structure. The storage structure is adjacent to the channel structure. The source line pillar and the bit line pillar are respectively adjacent to opposite sidewalls of the channel structure. The first gate does not vertically overlap with the channel structure.

According to some example embodiments, an integrated circuit includes a first inter-wiring insulating film on a substrate, a first and second wiring patterns spaced apart from each other on the first inter-wiring insulating film, a first etch stop layer on the first inter-wiring insulating film, the first and second wiring patterns, and a second inter-wiring insulating film on the first etch stop layer. Each of the first and second wiring patterns includes a first lower pattern in the first inter-wiring insulating film, and a first upper pattern on an upper surface of the first inter-wiring insulating film. The first etch stop layer extends along profiles of the upper surface of the first inter-wiring insulating film, and a side face and an upper surface of the first upper pattern. The second inter-wiring insulating film defines a first void between the first wiring pattern and the second wiring pattern.

A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.