A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

The on-resistance of a semiconductor device is reduced. A package structure composing the semiconductor device includes a die pad, a plurality of leads, a first semiconductor chip having a power transistor and mounted on the die pad, and a second semiconductor chip including a control circuit for controlling the power transistor and mounted on the first semiconductor chip. Here, a source pad of the first semiconductor chip is electrically connected to a first lead and a seventh lead of the plurality of leads via a clip made of a material which is copper as a main component, and the width (and cross-sectional area) of the clip is larger than the width (and diameter) of a wire in plan view.

A method for mounting a fin system in a power module includes: sintering a fin system to a first base substrate, the fin system comprising a plurality of fins attached to and extending away from a base plate; sintering a first power switch component to the first base substrate; sintering a second power switch component to a second base substrate; and soldering a heat dissipation element to the second base substrate.

According to one embodiment, a semiconductor device includes a semiconductor chip, a first conductor which includes a first portion exposed from a first surface of a sealing resin facing to a first direction, a second portion projecting from a second surface of the sealing resin facing to a second direction, and a bent portion connecting the first portion and the second portion, a second conductor exposed from a third surface of the sealing resin opposed to the first surface and having a thickness in the first direction which is greater than a thickness of the first conductor, a third conductor provided between the semiconductor chip and the first conductor, a first bonding material which bonds the semiconductor chip and the second conductor, a second bonding material which bonds the semiconductor chip and the third conductor, and a third bonding material which bonds the third conductor and the first conductor.

A semiconductor chip includes a first electrode provided farther in a first direction than the first lead frame and is electrically coupled to a first lead frame, and a second electrode. A first conductor electrically coupled to the second electrode. A second lead frame is aligned with the first lead frame at a position farther in a second direction than the first lead frame and includes a first terminal and a plate portion connected to the first terminal. The plate portion is electrically coupled to the first conductor and has an inclination over a first surface on a side in the first direction and a first side surface on a side in the second direction. A resin covers a part of the first lead frame, the semiconductor chip, the first conductor, and the plate portion and a part of the first terminal.

A semiconductor device includes a semiconductor element, a first lead including a die pad portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The die pad portion includes a first obverse surface facing a first side in a thickness direction and supporting the semiconductor element, a first reverse surface facing a second side in the thickness direction, a first side surface facing a first side in a first direction perpendicular to the thickness direction, and a plurality of first recesses each recessed from both the first reverse surface and the first side surface. The first reverse surface is exposed from the sealing resin, and the first recesses are arranged at intervals in a second direction perpendicular to the thickness direction and the first direction.

A semiconductor device includes a first lead including a base portion, a semiconductor element mounted on one side in a thickness direction of the base portion and having a first electrode disposed on the one side in the thickness direction and a second electrode disposed on the other side in the thickness direction, a second lead spaced apart from the base portion in a first direction orthogonal to the thickness direction, a first conductive member including a first portion bonded to the first electrode and a second portion bonded to the second lead and electrically connected to the first electrode and the second lead, a first bonding layer interposed between, and bonded to the base portion and the second electrode, and a second bonding layer interposed between, and bonded to the first electrode and the first portion. The first bonding layer includes a sintered metal.

According to one embodiment, there is provided a semiconductor device including a chip, and a gate electrode connected to a gate electrode pad provided on the chip. The gate electrode includes an external exposed portion having an external exposed surface that is flush with an external exposed surface of a sealing resin, and a gate electrode pad connection portion continuous with the external exposed portion and connected to the gate electrode pad, the gate electrode pad connection portion including a portion sandwiched between the gate electrode pad and a part of the sealing resin.

Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

The present disclosure proposes a semiconductor device, as well as a method for manufacturing such a semiconductor device, and related to a method of generating a dual exposed drain with common gate and source clip-bonded package for reverse battery protection. The semiconductor device includes a first lead frame with an external first lead frame terminal and a first die paddle, a second lead frame with an external second lead frame terminal and a second die paddle, a common clip with an external source clip terminal, a two source contacts, a common gate clip with an external common clip gate terminal, a clip contact and a gate clip contact, a first semiconductor die with a first die gate terminal, a first die source terminal, and a first die drain terminal, a second semiconductor die with a second die gate terminal, a second die source terminal, and a second die drain terminal.