The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.

An apparatus, system, and method for a die seal layout design to improve adhesion of a polyimide layer to a passivation layer in semiconductor packaging is disclosed. The apparatus may include an outer seal ring on a semiconductor die. The apparatus may also include an inner seal ring on a portion of the semiconductor die. The apparatus may further include a trench between the outer seal ring and the inner seal ring. The apparatus may include a passivation layer covering the semiconductor die including the outer seal ring and the inner seal ring. The apparatus may additionally include a polyimide layer covering a portion of the passivation layer over the inner seal ring and a portion of the trench.

A semiconductor package may include a package substrate including a chip mounting region; a semiconductor chip on the chip mounting region of the package substrate; a molding member on the semiconductor chip and the package substrate, the molding member including at least one marking groove in an upper surface of the molding member; and at least one marking pattern in the at least one marking groove.

An encapsulated semiconductor package is proposed, including a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet includes a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.

An encapsulated semiconductor package is proposed, including a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet includes a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.

A fan-out type packaging method includes: preparing a carrier substrate, where front and back sides of the carrier substrate are respectively provided with removable structures, forming redistribution layers on the front and back sides of the carrier substrate; mounting chips on the front and back sides of the carrier substrate; removing the carrier substrate and performing cutting to obtain a packaged chip. The present disclosure adopts a packaging process involving simultaneous processing on both sides, forming a symmetrical structure on the front and back sides. This may offset bending, dimensional instability, and other phenomena caused by performance differences between multilayer polymer materials and metal materials; the pre-redistribution layer fan-out packaging process adopted by the present disclosure may address precision issues of high-density wiring fan-out packaging. Additionally, the dual-sided structure may effectively offset warping caused by multilayer wiring.

A fan-out type packaging method includes: preparing a carrier substrate, where front and back sides of the carrier substrate are respectively provided with removable structures, forming redistribution layers on the front and back sides of the carrier substrate; mounting chips on the front and back sides of the carrier substrate; removing the carrier substrate and performing cutting to obtain a packaged chip. The present disclosure adopts a packaging process involving simultaneous processing on both sides, forming a symmetrical structure on the front and back sides. This may offset bending, dimensional instability, and other phenomena caused by performance differences between multilayer polymer materials and metal materials; the pre-redistribution layer fan-out packaging process adopted by the present disclosure may address precision issues of high-density wiring fan-out packaging. Additionally, the dual-sided structure may effectively offset warping caused by multilayer wiring.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.