Disclosed herein are chip packages having stiffeners and methods for making the same. In one example, a chip package includes a substrate, an integrated circuit (IC) die complex, a spacer, and a stiffener. The IC die complex is mechanically connected to the substrate. The spacer is formed on a top surface of the substrate outward of the IC die complex. The stiffener includes a ring base and a flange that extends inward from the ring base. The ring base has a bottom surface that is attached to the top surface of the substrate. The flange has a bottom surface attached to the top surface of the spacer. The attachment to the stiffener at inner and outer locations provides enhanced resistance to warpage.

Provided is a semiconductor package, the semiconductor package including: a package substrate having an upper surface on which a plurality of bonding pads are arranged; a semiconductor chip disposed on the package substrate, and having an upper surface on which a plurality of chip pads are arranged; an adhesive layer extending onto the upper surface of the package substrate between the semiconductor chip and the package substrate; a dam structure disposed around the adhesive layer, and surrounding a side surface of the adhesive layer; and external connection bumps disposed below the package substrate, and electrically connected to the plurality of bonding pads, wherein the external connection bumps are located below a region covered by the adhesive layer of the package substrate, and an area of the adhesive layer is greater than an area of a region in which the external bumps are disposed.

A wafer structure comprises a semiconductor wafer having a first side opposite a second side in a longitudinal direction. The wafer structure also comprises active circuitry formed on the first side of the semiconductor wafer. The active circuitry demarcates a voltage boundary between a first voltage zone and a second voltage zone in the semiconductor wafer. The wafer structure further includes an insulation layer including an insulation coating and an insulation barrier. The insulation coating is formed on the second side of the semiconductor wafer and extends to an insulation surface in the longitudinal direction. The insulation barrier extends from the insulation surface to the first side of the semiconductor wafer at the voltage boundary. The wafer structure yet further includes a conductive coating layer formed proximate to the insulation surface of a conductive coating material.

A package substrate based on a molding process may include an encapsulation layer, a support frame located in the encapsulation layer, a base, a device located on an upper surface of the base, a copper boss located on a lower surface of the base, a conductive copper pillar layer penetrating the encapsulation layer in the height direction, and a first circuit layer and a second circuit layer over and under the encapsulation layer. The second circuit layer includes a second conductive circuit and a heat dissipation circuit, the first circuit layer and the second conductive circuit are connected conductively through the conductive copper pillar layer, the heat dissipation circuit is connected to one side of the device through the copper boss and the base, and the first circuit layer is connected to the other side of the device.

An electronic device includes a three-dimensionally non-planar mold body defining at least part of one of a non-planar side surface and an opposed non-planar side surface of the electronic device, an electrically conductive structure provided on one of the non-planar side surface and the opposing non-planar side surface, and at least one electric entity at least partially inside of the three-dimensionally non-planar mold body.

A semiconductor device may include a semiconductor substrate, an element layer on the semiconductor substrate, a wiring layer on the element layer, and a buffer layer provided between the semiconductor substrate and the element layer or between the element layer and the wiring layer. The buffer layer may include a first buffer layer including a plurality of first voids spaced apart from each other and a second buffer layer provided on the first buffer layer. The buffer layer includes: a first buffer layer including a plurality of first voids spaced apart from each other, and a second buffer layer provided on the first buffer layer and including a plurality of second voids spaced apart from each other, The plurality of second voids are disposed at a different height level than the plurality of first voids. The plurality of second voids include a plurality of pairs of adjacent second voids. In a plan view, each of the first voids of the buffer layer is disposed between a corresponding one of the plurality of pairs of adjacent second voids.

The present invention provides an electronic or electrical device or component thereof comprising a cross-linked polymeric coating on a surface of the electronic or electrical device or component thereof; wherein the cross-linked polymeric coating is obtainable by exposing the electronic or electrical device or component thereof to a plasma comprising a monomer compound and a crosslinking reagent for a period of time sufficient to allow formation of the cross-linked polymeric coating on a surface thereof.

A semiconductor package includes a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip, a first bonding layer structure between the second semiconductor chips and including a first bonding pad structure, and a filling pattern contacting at least a portion of each of the second semiconductor chips and including silicon oxide or polymer. A sidewall of the filling pattern is aligned with a sidewall of the first semiconductor chip in the vertical direction. The first bonding layer structure includes first and second bonding layers contacting each other. The first bonding pad structure includes first and second bonding pads in the first and second bonding layers, respectively, and contacting each other. The first bonding layer contacts an upper surface of a lower one of the second semiconductor chips. The second bonding layer contacts a lower surface of an upper one of the second semiconductor chips.

A metal oxide particle material contains a metal oxide as a main component and has: a D50 of 1.0 m or more and 5.0 m or less, the D50 being obtained by measuring a laser diffraction particle size distribution; a specific surface area of 1.0 m.sup.2/g or more and 30 m.sup.2/g or less; a coarse particle content of 300 ppm or less, the coarse particle content being a content of coarse particles having a particle diameter of 5 m or more; and a hollow particle content of 4000 particles/10 mg or less, the hollow particle content being a content of hollow particles having a particle diameter of 5 m or more. When a resin material is filled with the metal oxide particle material at a solid concentration of 60% by mass, a resultant resin composition has a viscosity of 170 Pa.Math.s or less (at a shear velocity of 1 s.sup.1).

The present disclosure concerns a method of manufacturing an electronic component and the obtained component, comprising a substrate, comprising the successive steps of: depositing a first layer of a first resin activated by abrasion to become electrically conductive, on a first surface of said substrate comprising at least one electric contact and, at least partially, on the lateral flanks of said substrate; partially abrading said first layer on the flanks of said substrate.