A high-density integrated device package may include two or more primary device dies arranged along a first plane, an inductor comprising an inductor core and an inductor coil, the inductor being fixedly connected to at least one of the primary device dies, and a dielectric substrate arranged along a second plane which is substantially perpendicular to the first plane. The integrated device package further includes a secondary device die (e.g., a power IC) electrically connected to the dielectric substrate such that an orientation of the secondary device die is substantially perpendicular to that of the two or more primary device dies, wherein the dielectric substrate is fixedly connected to the inductor core, and wherein the dielectric substrate is electrically connected to at least one of the primary device dies by an edge connector.

An implantable integrated circuit medical device platform having integral and monolithic circuit traces. The platform allows for implanting the device into a mammalian body single and multi-functional interface devices for sensing, monitoring stimulating and/or modulating physiological conditions within the body. Microelectronic circuitry may be integrated onto the platform or may be joined as modular components to the platform.

Methods, systems, and devices for a stacked semiconductor system are described. The stacked semiconductor system may include a semiconductor die on a redistribution layer (RDL) and a polymer material at least partially surrounding the semiconductor die. A silicon nitride material may be above the semiconductor die and on the polymer material. A logic die may be hybrid bonded with a bonding material on the silicon nitride material. And a conductive post may extend at least partially through the silicon nitride material and the polymer material and may couple the logic die with the RDL.

A resin composition containing a bismaleimide compound (A) containing a constituent unit represented by the following formula (1) and maleimide groups at both ends of the molecular chain, a radical polymerizable resin or compound (B) other than the bismaleimide compound (A), and a curing accelerator (C), wherein the radical polymerizable resin or compound (B) contains at least one selected from the group consisting of a citraconimide group, a vinyl group, a maleimide group, a (meth)acryloyl group and an allyl group. ##STR00001##

A power semiconductor module arrangement comprises a substrate comprising a dielectric insulation layer, and a first metallization layer attached to the dielectric insulation layer, at least one semiconductor body mounted on the first metallization layer, and a first layer comprising an encapsulant, the first layer being arranged on the substrate and covering the first metallization layer the at least one semiconductor body, wherein the first layer is configured to release liquid or oil at temperatures exceeding a defined threshold temperature.

A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

A power semiconductor package includes a substrate, a power semiconductor chip arranged on the substrate, and an encapsulant encapsulating the power semiconductor chip. The encapsulant includes a voltage stabilizing additive. The voltage stabilizing additive is configured to minimize or eliminate partial discharges within the encapsulant.

A semiconductor package includes a base chip including a semiconductor body and a through-electrode structure penetrating through the semiconductor body and having a protrusion portion protruding upwardly of the semiconductor body, an insulating pattern on a side surface and an upper surface of the base chip, a chip stack on the base chip and the insulating pattern, and an encapsulant on the insulating pattern and covering at least a portion of the chip stack. The insulating pattern includes a first insulating portion on a side surface of the semiconductor body, and a second insulating portion on an upper surface of the semiconductor body and covering a side surface of the protrusion portion of the through-electrode structure. The insulating pattern includes an inorganic insulating material, and the encapsulant includes an organic insulating material.

The present invention relates to a semiconductor device including: a semiconductor substrate having: an active region through which a main current flows; and a termination region around the active region; a polyimide film disposed in the active region and the termination region; and a passivation film disposed as a film underlying the polyimide film, wherein the termination region includes, in order from a side of the active region, a breakdown voltage holding region and an outermost peripheral region, the polyimide film is disposed except for a dicing remaining portion of the outermost peripheral region, and the passivation film is disposed, as the underlying film, at least in a region where the polyimide film is disposed.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.