In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

The present application provides a film containing: a compound (A) containing at least one selected from the group consisting of a maleimide compound and a citraconimide compound; an organic peroxide (B) containing at least one selected from the group consisting of organic peroxides represented by specific formulae; and a hydroperoxide (C).

The present application provides a film containing: a compound (A) containing at least one selected from the group consisting of a maleimide compound and a citraconimide compound; an organic peroxide (B) containing at least one selected from the group consisting of organic peroxides represented by specific formulae; and a hydroperoxide (C).

A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.

A semiconductor package may include a first semiconductor die having a first width; a second semiconductor die on the first semiconductor die, the second semiconductor die having a second width that is smaller than the first width; and a mold layer at least partially covering a side surface of the second semiconductor die, and a top surface of the first semiconductor die, wherein the first semiconductor die comprises at least one first detection pattern, the at least one first detection pattern being on the top surface of the first semiconductor die and in contact with a bottom surface of the mold layer.

Some example embodiments are directed to a semiconductor device including a substrate including a chip region and a peripheral region, a circuit wiring layer on the chip region of the substrate, an interlayer insulating layer on the chip region of the substrate covering the circuit wiring layer, and extending on the peripheral region of the substrate, a chip pad on the interlayer insulating layer on the chip region, and connected to the circuit wiring layer, and a test pad on the interlayer insulating layer on the peripheral region. A thickness of the test pad is less than a thickness of the chip pad in a direction vertical to an upper surface of the substrate.

The present application relates to the technical filed of semiconductor chip nanofabrication, provides a method for preparing a chip embedded composite for electron beam lithography. The preparation method includes: providing a composite structure, the composite structure including a first substrate, a conductive layer disposed on a surface of the first substrate and a chip array disposed on a surface of the conductive layer away from the first substrate; arranging a protective layer on an outer surface of the chip array, where the protective layer covers the chip array; encapsulating and curing the composite structure and the protective layer by a polymer solution; removing the protective layer to obtain the chip embedded composite.

Provided is a curable composition having excellent workability and being capable of forming a cured product having super heat resistance by curing. The curable composition of the present disclosure includes a curable compound represented by Formula (1) below and a radical polymerization initiator. In the following formula, R.sup.1 and R.sup.2 each represent a curable functional group, and D.sup.1 and D.sup.2 each represent a single bond or a linking group. L represents a divalent group having a repeating unit containing a structure represented by Formula (I) below and a structure represented by Formula (II) below. Ar.sup.1 to Ar.sup.3 each represent an arylene group or a group in which two or more arylene groups are bonded via a single bond or a linking group. X represents CO, S, or SO.sub.2, and Y represents S, SO.sub.2, O, CO, COO, or CONH. n represents an integer of 0 or greater. ##STR00001##

There is provided a semiconductor package. The semiconductor package includes: a semiconductor chip; a mold configured to encapsulate the chip; a redistribution layer; and an optical device electrically connected to the chip through the redistribution layer. The mold is formed with an optical path passing through the mold, and light is input to or output from the optical device through the optical path.

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.