The present disclosure provides an electronic device including a first electronic unit, a second electronic unit, a circuit layer, a protection layer, and a flexible member. The first electronic unit is electrically connected to the second electronic unit through the circuit layer. The protection layer is disposed corresponding to the first electronic unit and the second electronic unit, and the protection layer has an opening. At least a portion of the flexible member is disposed in the opening. The protection layer has a first Young's modulus, the flexible member has a second Young's modulus, and the first Young's modulus is greater than the second Young's modulus.

An electronic power module is disclosed that forms external electrical connections without the use of a lead frame. Instead, various types of external connectors can be used, such as a press-fit pin assembly and an integrated connection post and power tap. Different methods of securing the external connectors to a multilayer substrate are also disclosed.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die having a first surface and an opposing second surface, where the first surface of the second die is electrically coupled to the first die by interconnects and the first surface of the third die is electrically coupled to the first die by a bonding material, and the bonding material includes titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; a first material, around the second die and the third die, having a non-planar surface; and a second material, on the non-planar surface of the first material and on the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.

A method of producing a power semiconductor device includes: providing a semiconductor body with a front side having a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; forming, at the front side, a first insulation layer above both the active region and the edge termination region; forming, at the first insulation layer, a first mask layer that covers the edge termination region at least partially and exposes the active region; removing a portion of the first insulation layer covering the active region; and while the first mask layer or a modified first mask layer or another mask layer covers the edge termination region, subjecting the edge termination region to a first implantation processing step to form, in the edge termination region, one or more doped semiconductor regions.

Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.

A device structure may be provided by: forming semiconductor devices and metal interconnect structures formed within dielectric material layers over a semiconductor substrate; forming metal pads in a topmost layer of the dielectric material layers; forming a passivation layer stack including a first dielectric diffusion barrier layer, a silicate glass layer, a second dielectric diffusion barrier layer, and a polymer layer; forming openings through the passivation layer stack over the metal pads; forming die bump structures on the metal pads; and dicing a wafer including the passivation layer stack, the dielectric material layers, and the semiconductor substrate along dicing channels into a plurality of semiconductor dies.

A heat-curable resin composition contains: (A) an aliphatic biscitraconimide compound represented by formula (1) defined as:

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wherein, in the formula (1), A is a divalent aliphatic hydrocarbon group having 2 to 12 carbon atoms; and (B) an epoxy resin containing two or more epoxy groups in one molecule. The amount of the component (A) is in the range of 20 to 95% by mass based on the total amount of the aliphatic biscitraconimide compound (A) and the epoxy resin (B).

A resin composition for molding includes an epoxy resin, a curing agent containing an active ester compound, an inorganic filler, and a porous polymer particle.

A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.