A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.

There are provided a semiconductor module capable of preventing the adhesion of an epoxy resin to a terminal to which at least one of a high current and a high voltage is supplied and a method for manufacturing a semiconductor module. A semiconductor module includes: a case having an inner wall defining a casting region and a peripheral edge portion arranged outside the inner wall; an intermediate terminal arranged in along side portion of a peripheral edge portion and having a fastening surface to which a cable is fastened; a structure arranged in a long side portion of the inner wall to be adjacent to the long side portion where the intermediate terminal is arranged and higher than the fastening surface; and a sealing section formed of an epoxy resin, having weld lines formed close to the side of the structure on a surface, and cast into a casting region to seal transistors.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

A substrate including a two-dimensional array of semiconductor dies and a rectangular grid of trenches that laterally extend along dicing channel regions may be provided. The rectangular grid of trenches may be filled with an elastic dielectric fill material. A combination of the two-dimensional array of semiconductor dies and a grid-shaped portion of the elastic dielectric fill material filling the rectangular grid of trenches may be diced along the dicing channel regions. A plurality of elastically padded semiconductor dies is formed. Each of the elastically padded semiconductor dies includes a respective singulated semiconductor die that includes semiconductor devices and metal bump structures located on dielectric material layers, and further includes an elastic protective material portion including a portion of the elastic dielectric fill material and laterally surrounding the dielectric material layers.

Provided is a semiconductor package, including a first chip, a second chip disposed on the first chip along a first direction, a first spacer film disposed below the second chip and covering at least a portion of a side surface of the first chip, and a first molding film disposed below the second chip and disposed to cover a side surface of the first spacer film, wherein the first spacer film and the first molding film include materials different from each other, and the side surface of the first spacer film is curved to be convex.

The present application provides a display device. The display device includes a display panel and an impact-resistance layer. The impact-resistance layer includes at least two sub-layers, two adjacent sub-layers of the sub-layers are bonded by an adhesive layer, the at least two sub-layers includes a first sub-layer and a second sub-layer between the first sub-layer and the display panel, the ratio of the elastic modulus of the first sub-layer to the elastic modulus of the second sub-layer is 20 to 300, and the material of the first sub-layer is different from the material of the second sub-layer.

A semiconductor device includes a plurality of semiconductor chips sequentially stacked on a substrate, an underfill layer between the plurality of semiconductor chips and between the substrate and a lowermost one of the plurality of semiconductor chips, and a molding resin extending around the plurality of semiconductor chips. The molding resin extends to a space between an uppermost one of the plurality of semiconductor chips and a semiconductor chip sequentially beneath the uppermost one of the plurality of semiconductor chips.

A semiconductor device includes a plurality of semiconductor chips sequentially stacked on a substrate, an underfill layer between the plurality of semiconductor chips and between the substrate and a lowermost one of the plurality of semiconductor chips, and a molding resin extending around the plurality of semiconductor chips. The molding resin extends to a space between an uppermost one of the plurality of semiconductor chips and a semiconductor chip sequentially beneath the uppermost one of the plurality of semiconductor chips.

An electronic component includes a plurality of laminated insulating layers, one or more surface conductors formed on a surface of the insulating layer, and an internal conductor formed at a boundary portion between the adjacent insulating layers. A thickness of the surface conductor is larger than a thickness of a thinnest layer of the insulating layers and larger than a thickness of the internal conductor.