H10W70/417

CHIP ON LEAD DEVICE AND MANUFACTURING METHOD
20260040959 · 2026-02-05 ·

An electronic device includes a non-conductive die attach film on a side of a conductive lead, a semiconductor die having a first side and a lateral side, the first side on the non-conductive die attach film, and the lateral side including striations, and a package structure enclosing the semiconductor die and a portion of the conductive lead. A method includes singulating portions of a non-conductive die attach film on a carrier, attaching a backside of a wafer to the singulated portions of the non-conductive die attach film, and singulating semiconductor dies of the wafer while the backside of the wafer is attached to the singulated portions of the non-conductive die attach film.

ISOLATION FOR CHIP ON LEAD DEVICE AND MANUFACTURING METHOD
20260040958 · 2026-02-05 ·

An electronic device includes a conductive lead, a semiconductor die, a package structure enclosing the semiconductor die and a portion of the conductive lead, and a non-conductive die attach film extending between the conductive lead and the semiconductor die and having a thickness less than 50 m. A method of fabricating an electronic device includes singulating portions of a non-conductive die attach film on a carrier, partially singulating prospective die areas from a front side of a wafer, removing wafer material from a back side of the wafer to separate a semiconductor die from the wafer, and attaching a backside the semiconductor die to a singulated portion of the non-conductive die attach film on the carrier.

Silver nanoparticles synthesis method for low temperature and pressure sintering

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a lead, a semiconductor substrate, a back-surface electrode provided between the semiconductor substrate and the lead, and a solder layer configured to connect the back-surface electrode and the lead. The back-surface electrode includes a silicide layer formed on a back surface of the semiconductor substrate, a bonding layer formed on the lead, a barrier layer formed on the bonding layer, and a stress relaxation layer formed between the silicide layer and the barrier layer. The stress relaxation layer is made of a first metal film containing aluminum as a main component or a second metal film containing gold, silver, or copper as a main component.

Universal Surface-Mount Semiconductor Package

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

LEADFRAME PACKAGE WITH METAL INTERPOSER
20260076235 · 2026-03-12 · ·

A semiconductor package includes a leadframe having a die pad and a plurality of pins disposed around the die pad, a metal interposer attached to a top surface of the die pad, and a semiconductor die attached to a top surface of the metal interposer. A plurality of bond wires with same function is bonded to the metal interposer. The die pad, the metal interposer and the semiconductor die are stacked in layers so as to form a pyramidal stack structure.

SEMICONDUCTOR PACKAGE SUBSTRATE INCLUDING GRAPHENE LAYER, METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE SUBSTRATE, AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR PACKAGE SUBSTRATE
20260076217 · 2026-03-12 ·

A semiconductor package substrate includes a base substrate including a conductive material, a die pad portion, and a lead portion, a metal catalyst layer disposed on the base substrate, and a graphene layer disposed on the metal catalyst layer, wherein the semiconductor package substrate has a Vickers hardness of 135 to 150.

ELECTRONIC DEVICES AND METHODS OF MANUFACTURING ELECTRONIC DEVICES

In one example, an electronic device include a substrate with a die paddle and a contact. An electronic component is coupled to the die paddle. A conductive connect includes a foot portion coupled to the contact and a connect plate portion coupled to the electronic component. The foot portion includes a top side, a bottom side, and an outward lateral side. A chamfer extends inward from the outward lateral side and extends to the bottom side. A conductive adhesive couples the foot portions to contact and covers the chamfer and the bottom side. An encapsulant covers the electronic component, the conductive connect, and at least portions of the substrate. The chamfer improves the bonding integrity between the conductive connect and the substrate. Other examples and related methods are also disclosed herein.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
20260083012 · 2026-03-19 ·

A semiconductor chip has a first semiconductor layer, a second semiconductor layer formed on an upper surface of the first semiconductor layer, and a semiconductor region formed in the second semiconductor layer. A trench is formed in the semiconductor region. An insulating film is formed on each of an upper surface of the second semiconductor layer and an inner surface of the trench. A polysilicon film is formed on the insulating film so as to embed an inside of the trench. A front surface electrode made of metal is formed on the polysilicon electrode, and a back surface electrode made of metal is formed on a lower surface of the first semiconductor layer. An impurity concentration of the second semiconductor layer located between the semiconductor region and the first semiconductor layer is lower than an impurity concentration of each of the first semiconductor layer and the semiconductor region.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a substrate, a die, a first bonding material, a second bonding material and a heat dissipation system. The die is connected to the substrate. The first bonding material is disposed on the substrate beside the die. The second bonding material is disposed on and covers the die. The heat dissipation system, having a bottom surface in contact with the second bonding material, is disposed on the second bonding material over the die and on the first bonding material on the substrate. The heat dissipation system is fixed to the substrate through the first bonding material. The bottom surface of the heat dissipation system is fixed to the die through the second bonding material with a bonding interface existing therebetween, and the bonding interface includes a first curved surface.