A semiconductor device having an improved bonding reliability of wire bonding is provided. The semiconductor device includes a semiconductor chip, a die pad, an inner lead, and a bonding wire. The semiconductor chip has a first lower surface, and a bonding pad provided on a first upper surface. The bonding pad has a second upper surface. The die pad has a third upper surface. The inner lead has a fourth upper surface. The semiconductor chip is mounted on the die pad such that the first lower surface faces the third upper surface. The bonding pad and the inner lead are electrically connected to each other via the bonding wire. In cross-sectional view, the second upper surface, to which the bonding wire is connected, of the bonding pad is located at the same height as the fourth upper surface, to which the bonding wire is connected, of the inner lead.

To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.

A lead frame includes a base comprising a bearing surface for bearing a chip. The bearing surface includes a soldering region, with a solder layer arranged in the soldering region. The solder layer is configured for fixing the chip on the bearing surface. The lead frame includes a groove provided on the bearing surface in a thickness direction of the base. The groove is located outside the soldering region and surrounds at least part of the soldering region along the outer periphery of the soldering region for receiving solder paste overflowed from the soldering region. A depth of the groove is based on a thickness of the base. A packaging structure including the lead frame and a packaging method using the lead frame are also provided.

A semiconductor device includes: a switch circuit chip and a control circuit chip, which are mounted on a first die pad; a first conductive bonding material configured to bond the first die pad and the switch circuit chip; and a second conductive bonding material configured to bond the first die pad and the control circuit chip. The switch circuit chip includes: a first semiconductor substrate bonded to the first die pad by the first conductive bonding material; and a first transistor and a second transistor, which have sources connected to each other. Both the first transistor and the second transistor are high electron mobility transistors including nitride semiconductors. The source of the first transistor and the source of the second transistor are electrically connected to the first die pad via the control circuit chip.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

In a general aspect, a semiconductor device assembly includes a conductive member, a conductive adhesive disposed on the conductive member, and a semiconductor die disposed on the conductive adhesive. The conductive adhesive couples the semiconductor die with the conductive member. The device assembly further includes a barrier included in the conductive member. The barrier is proximate to an edge of the semiconductor die and configured to inhibit outflow of the conductive adhesive.

A package includes an at least partially electrically conductive front-side connection body and an electronic component having an epitaxial layer and being assembled with the front-side connection body. A distance between the epitaxial layer and the front-side connection body is less than 50 m. A method of manufacturing the package is also described.

A semiconductor chip is provided. The semiconductor chip may include a front side including a control chip contact and a first controlled chip contact, a back side including a second controlled chip contact, a backside metallization formed over the back side in contact with the second controlled chip contact, and a stop region extending at least partially along an outer edge of the back side between a contact portion of the backside metallization and the outer edge of the back side. The contact portion is configured to be attached to an electrically conductive structure by a die attach material, a surface of the stop region is recessed with respect to a surface of the contact portion, and/or the surface of the stop region has a lower wettability with respect to the die attach material than the contact portion.

A lead frame including a die pad having a first surface and a second surface opposite the first surface, a lead having a third surface flush with the first surface and a fourth surface opposite the third surface, and a link portion connecting the die pad and the lead, wherein the link portion includes a first portion that surrounds the die pad between the die pad and the lead in a plan view, wherein the first portion has a fifth surface flush with the first surface and the third surface, and has a sixth surface opposite the fifth surface, wherein the second surface is closer to a plane containing the first surface, the third surface, and the fifth surface than is the fourth surface, and wherein the sixth surface is closer to the plane containing the first surface, the third surface, and the fifth surface than is the second surface.

A semiconductor device can include: a semiconductor chip including a first and second surface, a first electrode on the first surface, an active area on the second surface, a second electrode on the second surface, and a third electrode on the second surface; a first conductive member in the active area of the semiconductor chip and electrically connected to the semiconductor chip; a second conductive member in a second area and isolated from the first conductive member, the second area an area in which, when viewed from above, with respect to a first area of the active area in which the first conductive member is not provided, circles sharing centers of shortest distances between an outer periphery of the first conductive member and an outer periphery of the active area can be drawn largest in the first area; and a lead terminal connected to the first conductive member.