The present invention provides a chip packaging structure and a chip packaging method. Compared with an existing method of joining an encapsulation layer with a dielectric layer, adhesion between the encapsulation layer and a chip in the present invention is increased, and the encapsulation layer is less likely to fall off under stress. Furthermore, during the packaging process, a passivation layer enables chips to be mutually fixed together, which can prevent the chips from being shifted during the encapsulation process, and thereby enhance the reliability of the final product and improve the yield of the final product.

A method and a tool for film deposition are provided. The method of film deposition includes holding a semiconductor device in a chamber by a holding component, wherein the chamber is defined by a showerhead and a pedestal, providing reacting gases by the showerhead from a bottom side of the chamber, and forming a first dielectric layer on a backside surface of the semiconductor device.

An electronic device is provided. An example electronic device includes: a semiconductor body of Silicon Carbide, having a surface having a first portion of the surface that defines an active region of the electronic device and a second portion of the surface that is external to the active region; a metallization extending on the first portion of the surface of the semiconductor body; a passivation layer extending on part of the metallization; and an adhesion layer, based on one or more carbon allotropes, extending on the passivation layer.

Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a GaN heterojunction structure disposed on a substrate. The GaN heterojunction structure includes a barrier layer disposed on a GaN layer. The semiconductor device further includes a source contact, a drain contact, and a gate electrode. The gate electrode is disposed above the GaN heterojunction structure and between the source contact and the drain contact. The semiconductor device still further includes a plurality of segments of dielectric material disposed on the barrier layer between the source contact and the drain contact.

An electronic chip including a semiconductor substrate in and on which an integrated circuit is formed at least one connection metallization of the integrated circuit formed on the side of a front face of the semiconductor substrate and a first passivation layer covering the front face of the semiconductor substrate, the first passivation layer including openings in line with the connection metallization of the integrated circuit The chip having a second passivation layer covering the side flanks of the semiconductor substrate, the second passivation layer being made of a parylene, and the first passivation layer and the second passivation layer being in contact with each other on the side of the front face of the semiconductor substrate. Methods of making a device are also provided.

Semiconductor devices including one or more hydrogen-blocking layers are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A p-doped III-N layer is disposed over the barrier layer in the gate region and a gate electrode is formed over the p-doped III-N layer. A first hydrogen-blocking layer is disposed over the gate electrode where the first hydrogen-blocking layer is configured to arrest diffusion of hydrogen into the p-doped III-N layer from a dielectric layer formed after forming the gate electrode.

A method for manufacturing a semiconductor device, the method including forming a fin type pattern including a lower pattern and an upper pattern on a substrate, the upper pattern including a plurality of sacrificial layers and a plurality of sheet patterns alternately stacked on the lower pattern; forming a field insulating film on the substrate and the fin type pattern such that the field insulation film covers side walls of the lower pattern; forming a passivation film on the field insulating film such that the passivation film extends along an upper surface of the field insulating film; and removing the plurality of sacrificial layers after forming the passivation film.

A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor has a GaN epi-layer, a source ohmic contact, a drain ohmic contact, a gate structure, a first metal electrode contact and a first passivation layer. The source ohmic contact and the drain ohmic contact are disposed on the epi-layer. The gate structure is disposed on the epi-layer and between the source ohmic contact and the drain ohmic contact. The first metal electrode contact is disposed above the gate structure. The first passivation layer is sandwiched between the first metal electrode contact and the gate structure.

A method includes forming a first sealing layer at a first edge region of a first wafer; and bonding the first wafer to a second wafer to form a wafer stack. At a time after the bonding, the first sealing layer is between the first edge region of the first wafer and a second edge region of the second wafer, with the first edge region and the second edge region comprising bevels. An edge trimming process is then performed on the wafer stack. After the edge trimming process, the second edge region of the second wafer is at least partially removed, and a portion of the first sealing layer is left as a part of the wafer stack. An interconnect structure is formed as a part of the second wafer. The interconnect structure includes redistribution lines electrically connected to integrated circuit devices in the second wafer.

A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a first upper pad arranged on an upper surface of the first semiconductor substrate, a first polymer layer arranged on the upper surface of the first semiconductor substrate, a second semiconductor chip mounted on the first semiconductor chip, the second semiconductor chip including a second semiconductor substrate and a second lower pad arranged under a lower surface of the second semiconductor substrate, wherein the first polymer layer has a horizontal width in a direction crossing the first polymer layer in a center region of the second semiconductor chip, as a first length, and has a horizontal width in a direction crossing two corner regions of the first polymer layer in corner regions of the second semiconductor chip, as a second length, wherein the second length is greater than the first length.