Provided is a semiconductor chip including a semiconductor chip including a semiconductor substrate including a first surface and a second surface opposite to the first surface, a wiring layer arranged on the first surface of the semiconductor substrate, a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate, a plurality of chip pads arranged on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes, and a passivation layer arranged on the second surface of the semiconductor substrate and in contact with side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer arranged on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.

A semiconductor device includes: a semiconductor layer; a vertical metal-oxide semiconductor (MOS) transistor; a protective film; a first wiring electrode connected to a source electrode of the vertical MOS transistor; and a second wiring electrode connected to a gate electrode of the vertical MOS transistor. A first perimeter structure is provided in a perimeter portion of the first wiring electrode in the plan view of the semiconductor layer, the first perimeter structure protruding upward of the semiconductor device and including the source electrode, the protective film, and the first wiring electrode that are stacked in stated order. A second perimeter structure is provided in a perimeter portion of the second wiring electrode in the plan view of the semiconductor layer, the second perimeter structure protruding upward of the semiconductor device and including the gate electrode, the protective film, and the second wiring electrode that are stacked in stated order.

A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

One of the semiconductor devices includes a semiconductor device includes a conductive pad, a passivation layer and a conductive pattern. The passivation layer surrounds the conductive pad and has a sidewall interfacing with a sidewall of the conductive pad. The conductive pattern is disposed in the passivation layer and electrically connected to the conductive pad, wherein a first surface of the conductive pattern interfacing with the passivation layer and the conductive pad has at least one turning point.

In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

A silicon wafer, a preparation method of the silicon wafer, and a passivation treatment solution is disclosed. The preparation method of the silicon wafer can include the following steps: providing a solar silicon ingot; cutting the solar silicon ingot with a first treatment solution to form a pretreated silicon wafer; degluing the pretreated silicon wafer with a second treatment solution to obtain a deglued silicon wafer; and cleaning the deglued silicon wafer with a third treatment solution to obtain the silicon wafer; wherein at least one of the first treatment solution, the second treatment solution and the third treatment solution comprises a non-metallic compound that is bonded with a silicon ion via a single bond.

The cavity filter system-in-package module comprises a substrate, a first flip chip, a second flip device, a film layer, and a plastic encapsulant, wherein the substrate is provided with a groove, which extends from an upper surface of the substrate towards the interior of the substrate down to the layer where a second layer pattern is located or below; the first flip chip is mounted or soldered within the groove; the second flip device is mounted or soldered on the upper surface of the substrate; the first flip chip and the second flip device are surrounded by a solder mask layer; and a continuous film layer is formed on the surface of the first flip chip and the solder mask layer, and the film layer on the surface of the second flip device and the solder mask layer is discontinuous.

A method of manufacturing a structure for power electronics which includes epitaxially growing a GaN semiconductor layer is provided. The method includes growing buffer layers formed of AlN and Al.sub.xGa.sub.(1-x)N, wherein 0<x<1, on a Si substrate before growing the semiconductor layer on the buffer layers. The method also includes growing deformation compensation layers formed of SiO.sub.2, SiC.sub.xN.sub.(1-x), SiN, SiC.sub.xO.sub.(1-x), SiC, SiN.sub.xO.sub.(1-x), Al.sub.2O.sub.3, and/or Cr.sub.2O.sub.3, wherein 0<x<1, on the substrate opposite the semiconductor layer. The deformation compensation layers compensate for deformation of the structure that occurs while growing the semiconductor and buffer layers and deformation that occurs while cooling the structure. The method further includes estimating epitaxial growth stress, interface stress, and thermal stress of the structure, and adjusting the temperature and or thickness of the layers based on the estimated epitaxial growth stress, interface stress, and/or thermal stress.

A semiconductor device includes a compound semiconductor channel layer disposed on a substrate and located in an active element region and a passive element region. A compound semiconductor barrier layer is stacked on the compound semiconductor channel layer and located in the active element region and the passive element region. A source electrode, a gate electrode and a drain electrode are disposed on the compound semiconductor barrier layer and located in the active element region to construct a high electron mobility transistor. In addition, a first terminal electrode, an intermediate electrode and a second terminal electrode are disposed on the compound semiconductor barrier layer and located in the passive element region to construct a resistor.

A semiconductor device includes: a semiconductor substrate on which a device is provided; a metal wire provided on an upper surface of the semiconductor substrate and connected to the device; a passivation film which is an inorganic insulating film covering a corner portion of the metal wire and includes an opening provided on an upper surface of the metal wire; and an organic protective film covering the metal wire exposed from the opening.