A wafer-level package includes an integrated circuit (IC) die with pads on its front side. Surrounding the die's edge sides and front side is a resin layer containing an activatable catalyst material. A first passivation layer is positioned with its back surface contacting the front of the resin layer adjacent the die's front side, and a first solder resist layer is placed with its back surface contacting the front of the passivation layer. The redistribution layer includes first activated portions of the resin layer near the pads, forming electrical connections from the pads to the resin's back surface. Second activated portions extend along the resin's back surface toward the edge sides, while third activated portions run along the resin layer surrounding the die's edge sides. A first interconnect structure extends from the second activated portions, through the passivation and solder resist layers.

Disclosed herein are a heterojunction field effect transistor that can improve operation characteristics by forming a dual insulator layer between a p-GaN layer and a gate electrode and a manufacturing method thereof. The disclosed heterojunction field effect transistor includes: a substrate; a buffer layer formed on the substrate; a channel layer formed on the buffer layer and including a two-dimensional electron channel; a source electrode and a drain electrode formed on the channel layer and spaced apart from each other; a barrier layer formed between the source electrode and the drain electrode and inducing a formation of the two-dimensional electron channel at an interface with the channel layer; a p-GaN layer formed on the barrier layer; a double insulator layer formed on the p-GaN layer and made of different materials; and a gate electrode formed on the double insulator layer.

A semiconductor package and a method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies.

A semiconductor package includes a package substrate including a plurality of bonding pads, a plurality of semiconductor chips mounted on an upper surface of the package substrate, and each including a plurality of pads, the plurality of pads including a power voltage pad, a ground voltage pad, and a first signal pad and a second signal pad adjacent to each other, a plurality of connection lines including a first signal line connecting the first signal pads to the first bonding pad, and a second signal line connecting the second signal pads to the second bonding pad, and a first dummy line disposed between the first signal line and the second signal line.

A method for developing a passivation film on a substrate with less than 10 atomic % of hydrogen includes providing the substrate within a processing station of a substrate processing system. A resultant passivation film is formed with less than 10 atomic % of hydrogen on the substrate by performing the following steps of depositing a passivation film sub-layer on the substrate, where the passivation film sub-layer lays on a semiconductor device layer or directly on a previously deposited passivation film sub-layer, and after depositing the passivation film sub-layer, performing a post plasma treatment to the passivation film sub-layer with at least one of nitrogen and argon to reduce hydrogen content within the passivation film sub-layer.

The technology of this application relates to a switching power module that includes a substrate, a die embedded in the substrate, and a packaging layer. The packaging layer covers an integrated circuit layout layer of the die. The packaging layer packages the integrated circuit layout layer of the die, the die includes a composite material layer covering the integrated circuit layout layer, and the composite material layer includes at least two material layers that have different functions. The at least two material layers include a first material layer covering the integrated circuit layout layer, the first material layer is a mixed layer of undoped silicate glass and tetraethyl orthosilicate, and the first material layer is filled in a gap between metal protrusions of the integrated circuit layout layer, thereby improving an isolation effect between the metal protrusions. The mixed layer of the undoped silicate glass and the tetraethyl orthosilicate has a good thermal stress effect.

A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

A high electron mobility transistor (HEMT) device including a substrate and a semiconductor stack is provided. The semiconductor stack comprises a lower channel layer, an insertion layer (ISL) positioned above the lower channel layer for confining electrons in the lower channel layer, an upper channel layer, an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer, and a barrier layer positioned above the IEL. The ISL and the IEL are formed above the lower channel layer and the upper channel layer respectively to create a first and second wide bandgap heterojunction. The ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer. The potential barrier prevents or reduces a flow of hot electrons.

A semiconductor device includes a collector electrode, a collector-side element trench structure, a collector-side gate pad, and a collector-side terminal trench structure. A side surface of the semiconductor substrate and the collector electrode surround the collector-side gate pad in a planar view, and the collector-side terminal trench structure penetrates the collector layer on the side surface side of the semiconductor substrate with respect to the connecting portion between the collector electrode and the collector layer in a cross-sectional view.

An oxide film coating solution, including a silane compound and an organic solvent in which the silane compound is dissolved, in which the silane compound is represented by Chemical Formula 1 or Chemical Formula 2. Chemical Formula 1 is (R).sub.nSi(R).sub.m, in which R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group, R is an alkyl, methoxy, ethoxy, chloro, or disilazane group, n and m are integers of 1 to 3, and n+m is 4. Chemical Formula 2 is (R.sub.3Si).sub.nN(H).sub.m, in which R is an alkyl having a carbon number of 1 to 20, amine, fluorine, chlorine, vinyl, sulfur, methacryl, acetoxy, isocyanurate, or alkyleneoxy group, n and m are integers of 0 to 3, and n+m is 3.