Patent classifications
H10W74/137
Method for fabricating the semiconductor memory device
A method for fabricating a semiconductor memory device may include the steps of: forming a stacked body on a source layer by alternately stacking a plurality of interlayer dielectric layers and a plurality of gate sacrificial layers; forming a plurality of channel holes through the stacked body, the channel holes each having a lower end extended into the source layer; forming a channel layer along the surfaces of the channel holes, the channel layer including a first region formed in the stacked body and a second region formed in the source layer; and forming a channel passivation layer in the first region to scale down the thickness of the channel layer of the first region.
Semiconductor device with protective protrusion
A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.
Nitride-based semiconductor device with gate protection layer and method for manufacturing the same
A nitride-based semiconductor device includes a first and second nitride-based semiconductor layers, two or more source/drain (S/D) electrodes, a gate electrode, a doped III-V semiconductor layer, a gate protection layer and a first passivation layer. The doped III-V semiconductor layer is disposed between the second nitride-based semiconductor layer and the gate electrode. The gate protection layer caps the gate electrode and the doped III-V semiconductor layer and is separated from the S/D electrodes. The first passivation layer covers the second nitride-based semiconductor layer and the gate protection layer and abuts against sidewalls of the S/D electrodes which are separated from the gate protection layer by the first passivation layer.