A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

A power electronics module, having a DBC PCB having power semiconductors arranged thereon, and a multilayered leadframe including at least two separate subframes. No power or control routing takes place on the PCB. A region of the load source subregion is arranged between the PCB and the gate source and kelvin source subregion and is in electrical contact with the power semiconductors, and an adjoining region is located outside the PCB. A region of the drain source subregion is in electrical contact with a drain terminal on the PCB, and an adjoining region is located outside the PCB. The gate source subregion and the kelvin source subregion have a region above the load source subregion at which said subregions are in electrical contact with the power semiconductors and have an adjoining region outside the PCB which is opposite the drain source subregion and has pins bent above the PCB.

A pre-molded leadframe includes a laminar structure having empty spaces therein and a first thickness with a die pad having opposed first and second die pad surfaces. Insulating pre-mold material is molded onto the laminar structure. The pre-mold material penetrates the empty spaces and provides a laminar pre-molded substrate having the first thickness with the first die pad surface left exposed. The die pad has a second thickness that is less than the first thickness. One or more pillar formations are provided protruding from the second die pad surface to a height equal to a difference between the first and second thicknesses. With the laminar structure clamped between surfaces of a mold, the first die pad surface and pillar formations abut against the mold surfaces. The die pad is thus effectively clamped between the clamping surfaces countering undesired flashing of the pre-mold material over the first die pad surface.

Implementations of a substrate may include a first set of tie bars; a second set of tie bars; and a plurality of leads coupled between the first set of tie bars and the second set of tie bars. The first set of tie bars may intersect with the second set of tie bars. Each intersection of the first set of tie bars and the second set of tie bars may be downset from the plurality of leads.

A method of manufacturing a semiconductor device with an attached battery is provided. The method includes affixing a semiconductor die to a die pad region of a first battery lead of a leadframe. The first battery lead of the leadframe is separated from a second battery lead of the leadframe. An encapsulant encapsulates the semiconductor die and portions of the first and second battery leads of the leadframe. The battery is affixed to an exposed portion of the first battery lead of the leadframe such that a first terminal of the battery is conductively connected to the first battery lead. An exposed portion of the second battery lead of the leadframe is bent to overlap a top surface portion of the battery such that a second terminal of the battery conductively connected to the second battery lead.

A semiconductor device comprises a semiconductor chip and an electrically conductive chip carrier, wherein the semiconductor chip is mounted on the chip carrier. The semiconductor device furthermore comprises an electrically conductive extension element mechanically connected to the chip carrier, wherein the extension element and the chip carrier are formed as an integral single piece. A part of the chip carrier which has the extension element is configured as an antenna.

A semiconductor device includes a support member, a semiconductor element and a sealing member. The semiconductor element is disposed on a first side in a thickness direction relative to the support member. The sealing member covers a part of the support member and the semiconductor element. The support member has a first surface facing a second side in the thickness direction and exposed from the sealing member. The first surface is formed with a first uneven region. In an example, the first uneven region has an arithmetic mean roughness between 0.2 m and 13 m. In an example, the first uneven region includes a plurality of uneven lines in an arc shape.

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

An electronic device includes a non-conductive die attach film on a side of a conductive lead, a semiconductor die having a first side and a lateral side, the first side on the non-conductive die attach film, and the lateral side including striations, and a package structure enclosing the semiconductor die and a portion of the conductive lead. A method includes singulating portions of a non-conductive die attach film on a carrier, attaching a backside of a wafer to the singulated portions of the non-conductive die attach film, and singulating semiconductor dies of the wafer while the backside of the wafer is attached to the singulated portions of the non-conductive die attach film.

The present disclosure discloses a method of fabricating a semiconductor integrated circuits package with solder wettable plating and relates to a semiconductor package substrate with side wettable flank (SWF) features and a method of manufacturing thereof. In particular, the disclosure relates to leadless semiconductor devices and an associated method of manufacturing such devices. An object of the present disclosure is to provide a manufacturing technique allowing full plating of the side flanks by conventional electro-plating with an external conductive media.