A semiconductor device comprises a lower structure; a plurality of semiconductor layers laterally oriented in a direction parallel to a surface of the lower structure; a plurality of bit lines connected an end of the semiconductor layers and extending in a direction perpendicular to the surface of the lower structure; word lines extending laterally in a direction crossing the semiconductor layers over the semiconductor layers; and a device isolation layer extending in the direction parallel to the surface of the lower structure to be disposed between the bit lines and the word lines and including air gaps.

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes first and second fins formed on a semiconductor substrate and laterally separated from each other by an isolation feature, the isolation feature formed of a dielectric material that physically contacts the semiconductor substrate; and a contact feature between the first and second fins and extending into the isolation feature thereby defining an air gap vertically between the isolation feature and the contact feature, the dielectric material of the isolation feature extending from the semiconductor substrate to the contact feature.

Techniques are provided herein to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine having an airgap. The airgap may constitute a majority of the total volume of the dielectric spine, this lowering the dielectric constant of the dielectric spine and decreasing parasitic capacitance. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source and drain regions. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction between the first and second semiconductor regions. The dielectric spine includes a dielectric liner adjacent to the sides of the first and second semiconductor regions. A remaining volume of the dielectric spine at least partially bound by the dielectric liner includes an airgap. A dielectric cap structure may be included over the airgap.

A semiconductor device includes a substrate having an insulating layer and a device layer disposed on the insulating layer, wherein the device layer includes an active region, a plurality of gate structures arranged parallel to each other on the active region, a recess formed in the active region located between adjacent two of the gate structures and extending through the device layer, an epitaxial layer filling the recess, and an air gap between a bottom surface of the epitaxial layer and a top surface of the insulating layer.

In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region in a gate space, one or more conductive layers are formed over the gate dielectric layer, a seed layer is formed over the one or more conductive layers, an upper portion of the seed layer is treated by introducing one or more elements selected from the group consisting of oxygen, nitrogen and fluorine, and a W layer is selectively formed on a lower portion of the seed layer that is not treated to fully fill the gate space with bottom-up filling approach.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base, a first fin, and a second fin over the base. The semiconductor device structure includes a first nanostructure and a second nanostructure over the first fin and the second fin respectively. The semiconductor device structure includes an isolation structure between the first fin and the second fin and between the first nanostructure and the second nanostructure. The isolation structure has an air gap. The isolation structure over the air gap has a first portion and a second portion, and there is a boundary between the first portion and the second portion. The semiconductor device structure includes an isolation layer over the base. The semiconductor device structure includes a first gate stack over the isolation layer and wrapped around the first nanostructure.

The present disclosure relates to semiconductor structures and, more particularly, to devices with airgap structures and methods of manufacture. The structure includes: a semiconductor substrate with a trap-rich region; one or more airgap structures within the semiconductor substrate; at least one deep trench isolation structure laterally surrounding the one or more airgap structures and extending into the semiconductor substrate; and a device over the one or more airgap structures.

A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.

A structure includes a first air gap including a first opening defined in a first dielectric layer and a second dielectric layer over the first opening and closing an end portion of the first opening. A second air gap may be over at least a portion of the first air gap. The second air gap includes a second opening defined in the second dielectric layer and a third dielectric layer over the second opening and closing an end portion of the second opening. The second air gap has a pointed lower end portion. In another version, the structure includes a first air gap in a first dielectric layer, a second dielectric layer over the first air gap, and a discrete dielectric member positioned in the second dielectric layer and aligned over the first air gap.

A method comprises following steps. A first multi-layer stack is formed over a substrate. The first multi-layer stack comprises first semiconductor layers and second semiconductor layers alternating with the first semiconductor layers. A third semiconductor layer is formed over the first multi-layer stack. A second multi-layer stack is formed over the third semiconductor layer. The second multi-layer stack comprises fourth semiconductor layers and fifth semiconductor layers alternating with the fourth semiconductor layers. The third semiconductor layer is replaced with an isolation nanostructure. The first semiconductor layers and fourth semiconductor layers are removed. A first gate structure is formed surrounding the first semiconductor layers. A second gate structure is formed surrounding the fifth semiconductor layers.