Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.

A method for fabricating semiconductor devices is disclosed. The method includes forming, on a first side of a substrate, a first stack and a second stack. The method includes etching, from the first side, a portion of the substrate interposed between the first and second stacks to form a recess. The method includes filling the recess with a dielectric material to form an isolation structure. The method includes forming, on the first side, one or more first interconnect structures over the first and second stacks. The method includes removing, from a second side of the substrate opposite to the first side, a remaining portion of the substrate. The method includes forming a via structure extending through at least the isolation structure. The method includes forming, on the second side, one or more second interconnect structures.

A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.

An isolator includes a substrate; a first insulating film on the substrate; a second insulating film on the first insulating film, a third insulating film on the second insulating film, a first interconnect in the second insulating film, and first and second coils. The first interconnect has a thickness equal to a film thickness of the second insulating film. The first coil extends in the first and second insulating films. The first coil has a length in the extending direction greater than the thickness of the first interconnect. The third insulating film is provided on the second insulating film, and covers the first interconnect and the first coil. The second coil is provided on the third insulating film, and faces the first coil via the third insulating film.

A method of making a silicon-on-insulator (SOI) device from a bulk silicon substrate and an SOI device are disclosed. In the method, a stack of a heteroepitaxial layer and a silicon epitaxial layer are formed on a bulk silicon substrate, and a first photolithography process is performed on the stack to form a first trench exposing the bulk silicon substrate. The first trench is filled with a first isolation dielectric, and a second photolithography process is performed on the stack to form a second trench. The first isolation dielectric and the second trench isolate the stack. Subsequently, the heteroepitaxial layer is removed from the stack, forming at least one cavity. Moreover, the at least one cavity is filled with a buried oxide layer. The buried oxide layer and the silicon epitaxial layer overlying the buried oxide layer form SOI substrate structures. SOI devices are formed on the SOI substrate structures.

The present invention provides a method for forming self-transformed support plates in shallow trench isolation for advanced semiconductor devices, in which after a photolithography process to define active areas on a silicon substrate, an additional photomask is implemented to add a support plate patterning layer in areas where silicon will be etched during a STI etching step to form STI trenches. Tiny silicon support plates inside the STI trenches are formed after the silicon etching. These silicon support plates may provide mechanical support to hold neighboring patterned strips where the active areas are defined or neighboring active areas islands, and preventing them from bending, deformed or shifting. An alignment of photomask pattern at following photolithography process is eased.

Methods, systems, and devices for multi-step etching in memory architectures are described. A semiconductor device may be formed based on multiple etching operations. A first set of cavities may be etched through one or more materials prior to formation of conductive materials in the semiconductor device. Each first cavity may be etched through at least a portion of a first channel and a second channel of a set of multiple channels of the semiconductor device. After a formation of the conductive materials, one or more second cavities may be etched through a portion of the first set of oxide filled cavities and a portion of the conductive materials. The one or more second cavities may complete a division of the semiconductor device into multiple subblocks.

A process can be implemented to form adjacent transistors separated by a shallow trench isolation (STI), where the STI is formed after forming gates and sources/drains of the transistors. The STI can be formed by an active area cut using a mask to form a rectangular opening for filling with a STI dielectric. Using an active area mask providing a rectangular-like shape after forming gate stacks and source/drains, a memory device can be constructed having transistors separated by a STI having a recess from active areas of the transistors by at most 50 nm.