The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base; forming a plurality of support layers on the base, where the support layers are configured to support a plate capacitor structure, extend along a first direction, and are arranged at intervals along a second direction, and the first direction intersects the second direction; forming a bottom electrode layer, where the bottom electrode layer at least covers sidewalls of the support layers; and forming a dielectric layer, the dielectric layer covering the bottom electrode layer.

A method for manufacturing a semiconductor structure includes operations as follows. A substrate is provided, and a mask layer is formed on the substrate. An etching process is performed to form a plurality of first trenches in the mask layer, where the first trench has an inverted trapezoid cross-sectional shape. An epitaxy layer is formed on the substrate, where the epitaxy layer is filled in each of the first trenches to form an active area. The mask layer is removed to form a plurality of second trenches, where the second trench is arranged between adjacent active areas, and the second trench has a regular trapezoid cross-sectional shape. A dielectric layer is filled in the second trench to form an isolation structure.

A semiconductor device includes: a channel having layers of silicon separated from each other; a metal gate in contact with the layers of silicon; source/drain regions adjacent to the metal gate; a frontside power rail extending through the layers of silicon; a dielectric separating the frontside power rail from the metal gate; a via-connect buried power rail extending through the dielectric and coupling the frontside power rail to the source/drain regions; and a backside power rail coupled to the frontside power rail. The layers of silicon are wrapped on three sides by the metal gate.

A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.

A semiconductor device includes a semiconductor layer, an electronic element and laterally separated trench isolation structures. The semiconductor layer includes an element region having an inner region, an outer region on opposite sides of the inner region, and a transition region that laterally separates the inner region and the outer region. The electronic element includes a first doped region formed in the inner region and a second doped region formed in the outer region. The trench isolation structures are formed at least in the transition region. Each trench isolation structure extends from a first surface of the semiconductor layer into the semiconductor layer.

Transistors with improved saturation drain current and methods for making such transistors are disclosed. The gate is formed in the shape of a longitudinal trench and a plurality of lateral trenches below the longitudinal trench. The resulting dual-recess structure increases the surface area of the gate, which permits additional charge carriers and increases the saturation drain current of the transistor. Such transistors can be useful in high voltage and medium voltage applications such as in display driver integrated circuits.

Methods for forming a CPODE structure with reduced leakage current are disclosed herein. The CPODE structure is formed by etching away a pair of fins and forming a pair of trenches in the substrate where the pair of fins was originally located. A leakage path may be present in the area between the pair of fins. The etching is performed by cycling continuously plasma etch until the trenches are formed. The plasma etch removes any byproducts that may be formed during the fin etch which could reduce or stop the etching of the fins, the area between the pair of fins, and the substrate.

A method for forming an isolation structure includes following operations. A trench is formed in a semiconductor substrate. A first insulating layer covering a bottom and sidewalls of the trench is formed. A charge-trapping layer is formed on the first insulating layer. The trench is filled with a second insulating layer. The charge-trapping layer include a material different from those of the first insulating layer and the second insulating layer.

The present technology includes methods and systems for forming advanced memory structures, and devices therefrom. Methods include forming a dummy material layer over a first sidewall, a second sidewall, and a bottom surface, of one or more features, where the first sidewall is spaced apart from the second sidewall and the bottom surface is disposed between the first sidewall and the second sidewall. Methods include filling a gap formed between the dummy material on the first sidewall and the low resistivity material on the second sidewall with a sacrificial isolation material. Methods include removing at least a portion of the bottom surface, exposing at least a portion of the dummy material and the sacrificial isolation material. Methods include removing the sacrificial isolation material and at least a portion of the dummy material and selectively depositing a conductive material on a remaining portion of the dummy material.

A high voltage semiconductor device isolation structure and a method of manufacturing the same prevent a silicon penetration region from being formed between a first STI region and the side wall of a DTI region so that the breakdown voltage characteristic of a device is prevented from being decreased due to electric field concentration on the penetration region, and a method of manufacturing the same.