A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.

A semiconductor device includes a substrate having a first conductivity type and an epitaxial layer disposed on the substrate. A first trench and a second trench are disposed in the epitaxial layer. A first body region and a second body region both having a second conductivity type are disposed in the epitaxial layer, and located on two sides of the first trench, respectively. A first source region and a second source region both having the first conductivity type are disposed on the first body region and the second body region, respectively. A first electrode is disposed in the first trench. A source contact structure includes a first portion disposed in the first trench and is electrically connected to the first source region and the second source region. A first gate is disposed in the second trench.

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

A semiconductor device including a substrate including a trench; an isolation structure including an inner wall oxide layer pattern, a liner pattern, and a filling insulation pattern stacked in the trench; and a gate structure on the substrate and the isolation structure, wherein the inner wall oxide layer pattern and the liner pattern are conformally formed on a surface of the trench, a top surface of the inner wall oxide layer pattern is lower than an upper surface of the substrate, and a boundary between an upper surface of the inner wall oxide layer pattern and an upper surface of the liner pattern has no step difference.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure on the substrate; a plurality of inner spacer layers on sidewalls of the gate structure; a plurality of outer spacer layers on the plurality of inner spacer layers; a plurality of air gaps between the inner spacer layers and the outer spacer layers; a bottom dielectric layer on the substrate and laterally surrounding the outer spacer layers; a bottom capping layer on the bottom dielectric layer, the inner spacer layers, the air gaps, the outer spacer layers, and the gate structure; a conductive layer on the bottom capping layer and including a plurality of conductive wires; a top capping layer positioned on the conductive layer; and a plurality of air spacers positioned between the conductive wires.

A method includes forming a stack of channel layers and sacrificial layers over a fin base, forming an isolation feature adjacent to the fin base and the stack, forming a dummy gate structure over the stack and the isolation feature, and forming a source/drain trench in the fin base and exposing sidewalls of the sacrificial layers. The sacrificial layers include a top portion and a bottom portion. The method further includes removing the top portion to form a top opening and the bottom portion to form a bottom opening, depositing a dummy layer in the top and bottom openings, selectively and partially recessing the dummy layer to form inner spacer recesses, forming inner spacer features, forming a source/drain feature, and replacing the dummy gate structure and the dummy layer in the top opening but not the dummy layer in the bottom opening with a metal gate structure.

A manufacturing method of a semiconductor device includes depositing, using a first atomic layer deposition, a first thin poly silicon layer on an active area, in which the active area includes a trench; depositing, using a second atomic layer deposition, a second thin poly silicon layer on the active area; and depositing, using a chemical vapor deposition, a poly silicon layer on the active area to form a poly silicon structure, in which a gas for the chemical vapor deposition includes disilane, a thickness of the poly silicon layer in a bottom of the trenches is substantially zero.

A semiconductor device includes an active pattern including a plurality of channel patterns in a first region, a gate electrode surrounding the channel patterns, a doped bottom pattern including a first well having a first conductivity type and a second well region at the same level as the first well region and having a second conductivity type in a second region, a device isolation layer between the active pattern and the doped bottom pattern, a first doped region in the first well region having a dopant concentration of the first conductivity type larger than that within the first well region, and a second doped region in the second well region having a dopant concentration of the second conductivity type larger than that within the second well region, wherein the first doped region and the second doped region are positioned higher than a bottom surface of the device isolation layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a gate structure on the substrate; a plurality of inner spacer layers on sidewalls of the gate structure; a plurality of outer spacer layers on the plurality of inner spacer layers; a plurality of air gaps between the inner spacer layers and the outer spacer layers; a bottom dielectric layer on the substrate and laterally surrounding the outer spacer layers; a bottom capping layer on the bottom dielectric layer, the inner spacer layers, the air gaps, the outer spacer layers, and the gate structure; a conductive layer on the bottom capping layer and including a plurality of conductive wires; a top capping layer positioned on the conductive layer; and a plurality of air spacers positioned between the conductive wires.