Methods, systems, and devices for shallow trench isolation spacers are described. In some examples, shallow trenches may be formed in a silicon wafer and one or more dielectric materials may be formed in the trenches. A portion of the dielectric material may subsequently be removed (e.g., etched) and a spacer material may be formed in the trenches. In some examples, portions of the spacer material may be removed (e.g., etched) and the trenches may be filled with the dielectric material. The resulting trench may include one or more spacers that isolate the dielectric material from a gate oxide or other materials formed above the silicon wafer.

A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

A method includes forming a trench in a semiconductor layer of a device wafer and depositing a liner on the trench sidewalls. The liner is removed from the trench bottom, and the trench is deepened anisotropically to form an extension fully along the trench, or locally by applying a mask. The semiconductor material is removed outwardly from the extension by etching to create a cavity wider than the trench and below the liner. A space formed by the trench and cavity is filled with electrically conductive material to form a buried interconnect rail comprising a narrow portion in the trench and a wider portion in the cavity. The wider portion can be contacted by a TSV connection, enabling a contact area between the connection and buried rail. The etching forms a wider rail portion at a location remote from active devices formed on the front surface of the semiconductor layer.

Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes: a substrate is provided; bit line contact holes spaced apart from each other, bit line contacts each in contact with a part of a respective one of the bit line contact holes, and bit line structures are formed on the substrate, where each of the bit line structures includes at least a conductive layer and an insulating cap layer, and the insulating cap layer is located on the conductive layer; first insulating layers completely filling the bit line contact holes are formed inside the bit line contact holes; and insulation structures with air interlayers are formed on two side walls of the bit line structures, where a height of each of the air interlayers is greater than a height of the conductive layer of each of the bit line structures.

A method for fabricating semiconductor devices is disclosed. The method includes forming, on a first side of a substrate, a first stack and a second stack. The method includes etching, from the first side, a portion of the substrate interposed between the first and second stacks to form a recess. The method includes filling the recess with a dielectric material to form an isolation structure. The method includes forming, on the first side, one or more first interconnect structures over the first and second stacks. The method includes removing, from a second side of the substrate opposite to the first side, a remaining portion of the substrate. The method includes forming a via structure extending through at least the isolation structure. The method includes forming, on the second side, one or more second interconnect structures.

A method for manufacturing a semiconductor structure includes the following operations. A base and a dielectric layer arranged on the base are provided. A first conductive pillar, a second conductive pillar and a third conductive pillar arranged in the dielectric layer are formed. A mask layer is formed. A portion of a thickness of the third conductive pillar is etched by using the third mask layer as a mask to form a third lower conductive pillar and a third upper conductive pillar stacked on one another, in which the third upper conductive pillar, the third lower conductive pillar and the dielectric layer are configured to form at least one groove. A cover layer filling the at least one groove is formed, in which the cover layer exposes the top surface of the third upper conductive pillar.