A semiconductor memory structure includes a first active region and a second active region adjacent to the first active region, an isolation structure surrounding the first active region and the second active region, a first bit line structure extending across the first active region, and a contact plug extending into the second active region. The isolation structure includes a first insulating material and a second insulating material disposed on the first insulating material. The first bit line structure includes a contact portion extending into the first active region. An upper surface of the first insulating material is positioned lower than a bottom of the contact portion.

A diode device includes a semiconductor substrate, isolation structures, and metal silicide layers. The semiconductor substrate includes a well region and first to third doped regions in the well region. The first and second doped regions have opposite conductivity types, and a conductivity type of the well region is the same as the conductivity type of the second doped region. The third doped region is between the first and second doped regions. A conductivity type of the third doped region is the same as the conductivity type of the first doped region, and a dopant concentration of the third doped region is greater than a dopant concentration of the first doped region. The isolation structures are in the semiconductor substrate and spacing the first to third doped regions apart from each other. The metal silicide layers are respectively over the first and second doped regions.

A method includes forming a shallow trench isolation region in a semiconductor substrate, forming a first protruding fin and a second protruding fin higher than, and on opposing sides of, the shallow trench isolation region, and forming a hard mask over the shallow trench isolation region. The hard mask includes a first portion closer to the first protruding fin and overlapping a first part of the shallow trench isolation region, and a second portion closer to the second protruding fin and overlapping a second part of the shallow trench isolation region. The method further includes patterning the hard mask to remove the second portion of the hard mask and leaving the first portion of the hard mask over the first part of the shallow trench isolation region, and forming a gate stack over the first portion of the hard mask.

A semiconductor device is provided which includes a pair of fork sheet transistors. Each fork sheet transistor includes a plurality of vertically stacked, spaced apart semiconductor material nanosheets and a gate all around (GAA) structure formed on the semiconductor material nanosheets. The semiconductor device also includes a dielectric pillar, composed of a first dielectric material and located between the pair of fork sheet transistors. The semiconductor device further includes: first inner spacer portions, composed of a second dielectric material, located between the dielectric pillar and inner edges of the semiconductor material nanosheets of each fork sheet transistor; and second inner spacer portions, composed of the second dielectric material, and located between each of the semiconductor material nanosheets, above the semiconductor material nanosheets and below the semiconductor material nanosheets.

A semiconductor device includes a semiconductor substrate including a first side, a second side, a sidewall connected to the first and second sides, and at least one protrusion protruded from the second side, devices disposed at the first side of the semiconductor substrate, and an interconnect structure disposed over the first side of the semiconductor substrate and electrically coupled to the devices. The protrusion and the semiconductor substrate are made of a same material

A method of forming a semiconductor device includes a number of operations. A first semiconductor fin and a second semiconductor fin is formed over a substrate. An isolation region is formed between the first semiconductor fin and the second semiconductor fin. A first passivation layer is formed over the isolation region. A gate structure is formed over the first passivation layer.

Disclosed herein are methods, devices and systems including a substrate, a first dielectric layer on top of the substrate, a second dielectric layer on top of the first dielectric layer, a first epitaxial semiconductor layer arranged between the first dielectric layer and the second dielectric layer, a second epitaxial semiconductor layer on top of the second semiconductor layer, and a third dielectric layer contacting the first dielectric layer, the second dielectric layer, the first epitaxial semiconductor layer and the second epitaxial semiconductor layer.

The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implantation region, and a distance between the first doped region and the second doped region is equal to or more than 0.6 m.