A semiconductor device has a substrate. A first electrical component and second electrical component are disposed over the substrate. A zero-ohm resistor is disposed over the substrate between the first electrical component and second electrical component. An encapsulant is deposited over the substrate, first electrical component, second electrical component, and first zero-ohm resistor. An opening is formed through the encapsulant to the first zero-ohm resistor. A shielding layer is formed over the encapsulant and into the opening.

An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A die placement system provides a tip body and die placement head to ensure planarity of a die to substrate without the need for calibration prior to each pick and place operation. A self-aligning tip incorporated into a tip body aids in die placement/attachment. This tip provides for global correction of planarity errors that exist between a die and substrate, regardless of whether those errors stem from gantry (i.e. die-side misalignment) or machine deck tool (i.e. substrate-side misalignment) misalignment.

A semiconductor package comprises a base substrate, a first semiconductor chip on the base substrate, a first dam structure which overlaps a corner of the first semiconductor chip from a plan view and is placed on the base substrate and a first fillet layer which is placed vertically between the base substrate and the first semiconductor chip, and vertically between the first dam structure and the first semiconductor chip.

In one example, an optoelectronic module may include a stack assembly including an electrical integrated circuit and an optical integrated circuit electrically and mechanically coupled to one another, an interposer electrically and mechanically coupled to the stack assembly, and an optical connector to optically couple the optical integrated circuit with an array of optical fibers.

A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Methods, apparatuses, and systems related to an apparatus configured to provide varied connection positions. The varied connection positions may be provided through an alternating pattern of pads and pedestals that are each configured to attach and electrically couple to complementary connection points on a connected device.