A component carrier includes a stack with electrically conductive layer structures and at least one electrically insulating layer structure. The electrically conductive layer structures have a higher density connection region and a lower density connection region, and a first component and a second component which are surface mounted on the stack. The first component and the second component are electrically coupled with each other by the higher density connection region.

An embodiment semiconductor device may include a semiconductor die; one or more redistribution layers formed on a surface of the semiconductor die and electrically coupled to the semiconductor die; and an active or passive electrical device electrically coupled to the one or more redistribution layers. The active or passive electrical device may include a silicon substrate and a through-silicon-via formed in the silicon substrate. The active or passive electrical device may be configured as an integrated passive device including a deep trench capacitor or as a local silicon interconnect. The semiconductor device may further include a molding material matrix formed on a surface of the one or more redistribution layers such that the molding material matrix partially or completely surrounds the active or passive electrical device.

A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

A semiconductor package may include a first semiconductor chip, second semiconductor chips stacked on the first semiconductor chip in a vertical direction, adhesive layers interposed between the first semiconductor chip and one of the second semiconductor chips and between the second semiconductor chips, and a molding member on the first semiconductor chip. Edges of the adhesive layers may be positioned inward from sidewalls of the second semiconductor chips. The molding member may cover at least sidewalls of the second semiconductor chips and sidewalls of the adhesive layers. The molding member may fill edge gaps defined by the sidewalls of the adhesive layers and edges of upper surfaces and lower surfaces of the second semiconductor chips.

An electronic module includes at least one electronic component including a first principal surface, first and second electrodes on the first principal surface, a wiring board including a second principal surface, third and fourth electrodes on the second principal surface, and a conductive resin portion. The conductive resin portion includes at least one first conductive resin portion joining the first and third electrodes, and at least one second conductive resin portion joining the second and fourth electrodes. The electronic module further includes at least one reinforcing resin portion that is disposed between at least one first and at least one second conductive resin portions and joins the first principal surface of the electronic component with the second principal surface of the wiring board.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

A package structure is provided, which includes a redistribution structure, an interposer substrate disposed over the redistribution structure, a first semiconductor die disposed between the redistribution structure and the interposer substrate, a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface of the redistribution structure, and a first protective layer surrounding the first semiconductor die.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.