A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

The present disclosure relates to a double-sided integrated circuit (IC) module, which includes an exposed semiconductor die on a bottom side. A double-sided IC module includes a module substrate with a top side and a bottom side. Electronic components are mounted to each of the top side and the bottom side. Generally, the electronic components are encapsulated by a mold compound. In an exemplary aspect, a portion of the mold compound on the bottom side of the module substrate is removed, exposing a semiconductor die surface of at least one of the electronic components.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.

A method is provided, including forming a wafer structure including a sacrificial layer between first and second substrates; forming first sacrificial structures within the second substrate in the spacing regions; forming second sacrificial structure within the second substrate; forming conductive vias through the second substrate in the die regions; forming dielectric layers over the second substrate and forming conductive features in the dielectric layers in the die regions; forming first windows through the dielectric layers and extending to the first sacrificial structures; forming second window through the dielectric layers and extending to the second sacrificial structure; forming a protective layer over the dielectric layers and filling the first windows; attaching a carrier substrate to the protective layer; removing the sacrificial layer, first sacrificial structures, and second sacrificial structure by flowing an etchant through the at least one second window; removing the protective layer; and detaching the carrier substrate.

A flip-chip bonding-based antenna packaging structure and its manufacturing method are provided. The flip-chip bonding-based antenna packaging structure includes a lead frame structure and a redistribution structure disposed above the lead frame structure. The redistribution structure includes a first surface and a second surface. The lead frame structure is disposed on the redistribution structure and includes a metal member, a first active element, and a passive element. The metal member includes a base portion, a first supporting portion on the base portion, and an extension portion adjacent to the first supporting portion. The extension portion extends from the base portion, and the first supporting portion is parallel to the extension portion. The first active element is disposed between the first supporting portion and the first surface. The passive element is disposed on the second surface and is electrically connected to the first active element.

A method and an apparatus for forming an electronic device is provided. The method comprises: providing a substrate; disposing at least one electronic component on the substrate via a solder paste; applying microwave radiation to the substrate to reflow the solder paste; applying a vacuum pressure to the substrate to remove voids formed within the solder paste during the reflowing of the solder paste; solidifying the solder paste into solder bumps between the substrate and the at least one electronic component.

An atmospheric pressure plasma apparatus and method are disclosed that operate with a multigas mixture to provide a high concentration of reactive neutral species for cleaning and activating the surfaces of substrates, including those with metal interconnects embedded in the substrate.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

A die package comprises a substrate comprising a solder pad element, a semiconductor die coupled to the substrate, a solder layer comprising a first solder material deposited on the solder pad element, the first solder material having a first melting temperature, and an interconnect ball comprising a second solder material deposited on the solder layer, the second solder material having a second melting temperature that is less than the first melting temperature.