An apparatus comprising a first substrate, a dam structure disposed on a first side of the first substrate, and an integrated circuit (IC) memory chip coupled to the first side of the first substrate by a plurality of first conductive members. A second substrate is coupled to a second side of the first substrate by a plurality of second conductive members. A lid coupled to the second substrate encloses the IC memory chip and the first substrate. A thermal interface material (TIM) is coupled between the lid and the dam structure.

Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillars that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillars are conductive wires. A package body encapsulates the electronic component and the conductive pillars. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent to the package body, which is electrically connected to the conductive pillars. In one embodiment, the electrical connection is made through the package body. In another embodiment, the electrical connection is made through the substrate.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

Electronic devices, electronic modules, and methods for manufacturing electronic devices and/or electronic modules are described herein. Some embodiments of the present invention may be directed to an electronic module that includes a multi-chip module (MCM) substrate having a first surface configured to be connected to a system printed circuit board and a second surface defining a central portion and a peripheral portion. The electronic module may include a main die positioned on the central portion of the second surface of the MCM substrate and in electrical communication with electrical traces of the MCM substrate. The electronic module may include MCM sockets positioned on the peripheral portion of the MCM substrate, where each MCM socket is configured to engage and support a mezzanine package substrate such that a main portion of the mezzanine package substrate extends beyond the peripheral portion of the MCM substrate.

A semiconductor package comprises a base chip, a plurality of semiconductor chips sequentially stacked on the base chip, bump structures between the base chip and a lowermost semiconductor chip of the plurality of semiconductor chips, and between the plurality of semiconductor chips, adhesive layers surrounding the bump structures between the base chip and the lowermost semiconductor chip of the plurality of semiconductor chips and between the plurality of semiconductor chips. The adhesive layers have a width equal to or less than a width of each of the plurality of semiconductor chips in a direction parallel to an upper surface of the base chip. At least one of the adhesive layers comprises a polymer resin having a hydrophilic group, a photosensitive compound physically bonded to the polymer resin, and an ionic material crosslinking the polymer resin.

Techniques are provided for fabrication of an electronic device. A methodology implementing the techniques according to an embodiment includes forming a plurality of thin film components on a wafer substrate. The method also includes cutting one or more of the thin film components from the wafer substrate and extracting the one or more of the thin film components from the wafer substrate. The method further includes depositing the extracted thin film components onto pads of a printed circuit board (PCB) assembly. The method further includes performing a solder reflow to electrically couple the one or more thin film components onto the pads of the PCB assembly. The thin film component comprises a release layer, solder layers, solder barrier layers, non-wetting solder barrier layers, a passivation layer, and a component function layer. The component function layer may provide a resistive function, a capacitive function, a diode function, or a thermocouple function.

In an embodiment, a device includes: a die stack over and electrically connected to an interposer, the die stack including a topmost integrated circuit die including: a substrate having a front side and a back side opposite the front side, the front side of the substrate including an active surface; a dummy through substrate via (TSV) extending from the back side of the substrate at least partially into the substrate, the dummy TSV electrically isolated from the active surface; a thermal interface material over the topmost integrated circuit die; and a dummy connector in the thermal interface material, the thermal interface material surrounding the dummy connector, the dummy connector electrically isolated from the active surface of the topmost integrated circuit die.

Techniques are provided for containing magnetic fields generated by an integrated switching package and for reducing electromagnetic interference generated from an integrated switching package.