A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects; a first integrated device coupled to the substrate through a first plurality of solder interconnects, wherein the first plurality of solder interconnects includes a first plurality of inner solder interconnects and a first plurality of perimeter solder interconnects; and a second integrated device coupled to the substrate through a second plurality of solder interconnects. The first integrated device is configured to be electrically coupled to the second integrated device through an electrical path. The electrical path comprises an inner solder interconnect from the first plurality of inner solder interconnects, at least one interconnect from the plurality of interconnects, and a solder interconnect from the second plurality of solder interconnects.

An electronic component mounting device (1) comprises: an electronic component supply unit (20) that supplies an electronic component having a bump electrode (EB); a transfer stage (31) that accumulates a flux (FX); a mounting stage (41) on which a substrate (BD) is placed; a plurality of heads that can each pick up an electronic component (CP); and a control unit (10) that controls movement of the plurality of heads. The control unit (10) is configured so as to cause each of the plurality of heads to function as a dipping head that dips the bump electrode (EB) of the electronic component (CP) into the flux (FX) accumulated on the transfer stage (31), or as a bonding head that mounts the electronic component (CP) to the substrate (BD) on the mounting stage (41) with the bump electrode (EB) interposed therebetween.

Methods of fabricating semiconductor devices and resulting bonded structures. An embodiment method includes tilting a plasma nozzle to an angle with respect to a substrate. The method includes applying, with the plasma nozzle, an oxidation gas onto a first side of at least one substrate-side copper bump on the substrate, forming an oxidized copper sidewall on the first side of the substrate-side copper bump. The method includes bonding a semiconductor chip to the substrate using the substrate-side copper bump.

In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed; multiple copper posts coupled to the device side of the semiconductor die; a substrate coupled to the multiple copper posts by solder joints, the substrate comprising: cylindrical copper pillars extending from the solder joints on a top surface of the substrate to a bottom surface of the substrate, the copper pillars having circular or ovoid bottom surfaces exposed to the bottom surface of the substrate; and a build-up film between and physically contacting the copper pillars. The package also includes a mold compound physically contacting the semiconductor die, the multiple copper posts, and the top surface of the substrate.

An electronic device includes a semiconductor die having a first side attached to a substrate, a first plate having a first portion attached to a second side of the semiconductor die and a second portion extending from the first portion away from the semiconductor die, a metal clip having a second clip portion coupled to a first conductive feature of the substrate, a third clip portion coupled to a second conductive feature of the substrate, and a first clip portion above and spaced apart from the first portion of the first plate that extends between the second and third clip portions, a magnetic molding compound package structure enclosing the metal clip, the semiconductor die, and the first portion of the first plate, and a second plate exposed outside the package structure and thermally coupled to the second portion of the first plate.

A device includes: a first substrate; a second substrate; interconnects bonding the first substrate to the second substrate; and a polymer brush-based underfill layer in a gap between the first substrate and the second substrate. A method includes: attaching initiator molecules to one or more surfaces in a gap between a first substrate and a second substrate of a bonded structure, where the first substrate and the second substrate are bonded by interconnects; growing polymer chains from the initiator molecules; and annealing the bonded structure to form an underfill layer from the polymer chains in the gap.

An electronic package, a packaging substrate and a fabricating method are provided, in which a conductive bump pad is formed on an electrical contact pad of the packaging substrate, so that when an electronic element is bonded to the packaging substrate via a solder material in a flip-chip process, the conductive bump pad can guide the flow of the solder material. Therefore, the problem of empty soldering caused by the solder material not effectively contacting with the electrical contact pad can be avoided.

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.

A semiconductor structure includes a first unit bonded assembly including a first memory die bonded to a first logic die by direct copper to copper bonding, where that the first logic die includes first through-substrate via structures laterally surrounded by first doped semiconductor well guard rings, and a second unit bonded assembly including a second memory die bonded to a second logic die by direct copper to copper bonding. The first unit bonded assembly is bonded to a second unit bonded assembly by solder balls.