A method of manufacturing an electronic device includes: providing a vapor generating chamber that accommodates a heat transfer fluid; providing a substrate stage within the vapor generating chamber, the substrate stage including a seating surface and suction passages penetrating the substrate stage to be open to the seating surface; loading a substrate on the substrate stage, wherein electronic components are disposed on the substrate via bumps; generating at least a partial vacuum in the suction holes to suction-support the substrate on the seating surface; heating the heat transfer fluid to generate saturated vapor within the vapor generating chamber; and soldering the bumps using the saturated vapor.

A semiconductor package includes a first redistribution substrate, a passive device mounted on a bottom surface of the first redistribution substrate, a first semiconductor chip disposed on a top surface of the first redistribution substrate, the first semiconductor chip including a through via disposed therein, a second semiconductor chip disposed on the first semiconductor chip, and a conductive post disposed between the top surface of the first redistribution substrate and a bottom surface of the second semiconductor chip and spaced apart from the first semiconductor chip. The conductive post is connected to the first redistribution substrate and to the second semiconductor chip. The conductive post overlaps with at least a portion of the passive device in a vertical direction normal to the top surface of the first redistribution substrate.

A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a first substrate, a first chip, a second chip, a first heat conductor and a second heat conductor, wherein the first substrate includes a cavity; the first chip is embedded in the cavity and includes a first connecting surface and a first heat-conducting surface that face away from each other; the second chip is disposed on a side of the first connecting surface and electrically connected to the first chip, a side of the second chip distal from the first chip includes a second heat-conducting surface on a side; and the first heat conductor is connected to the first heat-conducting surface, and the second heat conductor is connected to the second heat-conducting surface. The first substrate includes a third connecting surface that is flush with the first connecting surface.

A multiple die package is described that has an embedded bridge to connect the dies. One example is a microelectronic package that includes a package substrate, a silicon bridge embedded in the substrate, a first interconnect having a first plurality of contacts at a first location of the silicon bridge, a second interconnect having a second plurality of contacts at a second location of the silicon bridge, a third interconnect having a third plurality of contacts at a third location of the silicon bridge, and an electrically conductive line in the silicon bridge connecting a contact of the first interconnect, a contact of the second interconnect, and a contact of the third interconnect each to each other.

Provided is a package structure, including a substrate, a chip on the substrate in a flip-chip manner, the chip including a circuit layer, and a side heat dissipator on a side of the chip, the side heat dissipator comprising a heat conduction material, wherein the side heat dissipator is electrically connected to the circuit layer.

A method for manufacturing an electronic package comprises providing at least one electronic component, the at least one electronic component including at least one non-groundable thermal output, providing a substrate in which a ground plane is enclosed in or supported by the substrate, defining at least one thermally conductive pathway extending between an interface exposed on the substrate and the ground plane such that the interface is electrically isolated from the ground plane, and mounting the electronic component to the substrate, the mounting including thermally coupling the output to the interface with at least one thermally conductive member.

A disclosed system is configured to bond a chip to a substrate and includes a chip processing subsystem that is configured to receive the chip and to expose the chip to a first plasma, and a substrate processing subsystem that is configured to receive the substrate and to expose the substrate to a second plasma. The system further includes a bonding subsystem that is configured to align the chip with the substrate, to force the chip and the substrate into direct mechanical contact with one another by application of a compressive force, and to apply heat to at least one of the chip or the substrate. Application of the compressive force and the heat thereby bonds the chip to the substrate. The first and second plasmas may include H.sub.2/N.sub.2, H.sub.2/Ar, H.sub.2/He, NH.sub.3/N.sub.2, NH.sub.3/Ar, or NH.sub.3/He and the chip and substrate may be maintained in a low oxygen environment.

An electronic structure, an electronic package and a manufacturing method thereof are provided, in which a carrier and an adhesive layer are used to support or fix the electronic structure and the electronic package, and double carriers are used to support or fix the electronic structure and the electronic package, thereby avoiding the warpage problem of the electronic structure and the electronic package.