A leadframe (10) comprises: a functional area (12) having a first standard electrode potential; and a non-functional area (14) adjacent to the functional area (12) and including a protective layer, the protective layer (16) having a second standard electrode potential lower than the first standard electrode potential and acting as a sacrificial anode to protect the functional area (12) as a cathode from corrosion/oxidation. Embodiments of the present disclosure may help to protect functions of the leadframe (10) from affections of corrosion/oxidization, etc.

Implementations of a semiconductor package may include one or more leads operatively coupled with one or more semiconductor devices; and a mold compound coupled to the one or more leads and exposing a flank of the one or more leads through a surface of the mold compound that may be oriented substantially perpendicularly to a longest length of the one or more leads. An exposed surface of the flank may be recessed into the surface of the mold compound. The exposed surface of the flank may include at least one curve.

A semiconductor package carrier structure is provided and includes a substrate body, a dielectric material, and a patterned circuit layer. The substrate body has a plurality of openings, a plurality of conductive pillars, and at least one die placement portion. The dielectric material is disposed in the plurality of openings. The patterned circuit layer is disposed on a surface of the substrate body. Side surfaces of the plurality of conductive pillars and the die placement portion are all in a concave arc shape. The patterned circuit layer includes a die placement pad corresponding to the die placement portion and a plurality of bonding pads corresponding to the plurality of conductive pillars. A method of manufacturing the semiconductor package carrier structure is further provided.

The present disclosure is directed to semiconductor packages manufactured utilizing a leadframe with varying thicknesses. The leadframe with varying thicknesses has a reduced likelihood of deformation while being handled during the manufacturing of the semiconductor packages as well as when being handled during a shipping process. The method of manufacturing is not required to utilize a leadframe tape based on the leadframe with varying thicknesses. This reduces the overall manufacturing costs of the semiconductor packages due to the reduced materials and steps in manufacturing the semiconductor packages as compared to a method that utilizes a leadframe tape to support a leadframe. The semiconductor packages may include leads of varying thicknesses formed by utilizing the leadframe of varying thicknesses to manufacture the semiconductor packages.

A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.

A method of forming a lead frame can include: providing a frame base; providing a substrate to support the frame base; and selectively etching the frame base to form first and second type pins. The first type pins are distributed in the central area of the lead frame, and the second type of the pins are distributed in the edge area of the lead frame. The first type pins are separated from the second type of the pins, and the first and second type pins are not connected by connecting bars. A pattern of a first surface of the first and second type pins is different from that of a second surface of the first and second type pins. The metal of the first surface is different from the metal of the second surface, and the second surface is opposite to the first surface.

A package construction includes: a die pad, and a suspension lead remaining portion connected to the die pad. Here, an offset portion is provided from a peripheral edge portion of the die pad to the suspension lead remaining portion. Also, the suspension lead remaining portion has: a first end portion connected to the die pad, and a second end portion opposite the first end portion. Further, the second end portion of the suspension lead remaining portion is exposed from the side surface of the sealing body at a position spaced apart from each of the upper surface and the lower surface.

An integrated circuit package includes a leadframe with leads delimiting a center cavity. The leads of the leadframe have upper surfaces with a surface texture or finish having a first surface roughness. A drop-in die pad is installed within the center cavity. The drop-in die pad has an upper surface with a surface texture or finish having a second surface roughness that is rougher than the first surface roughness. An integrated circuit die is mounted to the upper surface of the drop-in die pad and electrical connections are formed between bonding pads of the integrated circuit die and the leads of the leadframe. An encapsulation body encapsulates the leadframe, drop-in die pad and electrical connections.

A semiconductor device has a substrate with a die mounting site and a plurality of leads. A first electrical component is disposed over a first surface of the die mounting site. A second electrical component is disposed over a second surface of the die mounting site opposite the first surface of the die mounting site. A first bond wire is coupled between the first electrical component and a first lead, and a second bond wire is coupled between the second electrical component and a second lead. A first encapsulant is deposited over the first electrical component, and a second encapsulant is deposited over the second electrical component with the leads exposed between the first encapsulant and second encapsulant. The leads are exposed from the first encapsulant and second encapsulant on a side of the semiconductor device.

The present disclosure discloses a method of fabricating a semiconductor integrated circuits package with solder wettable plating and relates to a semiconductor package substrate with side wettable flank (SWF) features and a method of manufacturing thereof. In particular, the disclosure relates to leadless semiconductor devices and an associated method of manufacturing such devices. An object of the present disclosure is to provide a manufacturing technique allowing full plating of the side flanks by conventional electro-plating with an external conductive media.