A package and method is disclosed. In one example, the package comprises a component assembly section, at least one electronic component being assembled with the component assembly section, at least one lead section being electrically coupled with the at least one electronic component and/or with the component assembly section, an encapsulant at least partially encapsulating the at least one electronic component and partially encapsulating the component assembly section and the at least one lead section so that part of the component assembly section and part of the at least one lead section are exposed beyond the encapsulant. A thermoplastic structure covers an exposed area of the component assembly section without covering an exposed area of the at least one lead section.

The disclosure is directed to wide band-gap semiconductor devices, such as power devices based on silicon carbide or gallium nitride materials. A power device die is attached to a carrier substrate or a base using sintered silver as a die attachment material or layer. The carrier substrate is, in some embodiments, copper plated with silver. The sintered silver die attachment layer is formed by sintering silver nanoparticle paste under a very low temperature, for example, lower than 200 C. and in some embodiments at about 150 C., and with no external pressures applied in the sintering process. The silver nanoparticle is synthesized through a chemical reduction process in an organic solvent. After the reduction process has completed, the organic solvent is removed through evaporation with a flux of inert gas being injected into the solution.

A low-inductance power module comprises a housing, upper-bridge MOSs, lower-bridge SBDs, lower-bridge MOSs, upper-bridge SBDs, output electrodes, a positive electrode and a negative electrode. A bottom plate is mounted inside the housing. An insulating substrate is mounted at the top of the bottom plate. A positive-electrode copper layer, a negative-electrode copper layer and an output-electrode copper layer are arranged on the upper surface of the insulating substrate. The output-electrode copper layer is divided into an upper-side output-electrode copper layer and a lower-side output-electrode copper layer.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

A semiconductor package substrate includes a base substrate including a conductive material, a die pad portion, and a lead portion, a metal catalyst layer disposed on the base substrate, and a graphene layer disposed on the metal catalyst layer, wherein the semiconductor package substrate has a Vickers hardness of 135 to 150.

A described example includes a method for fabricating an integrated circuit (IC) device. The method can include forming a mask on a surface of a multi-layer substrate, in which the multi-layer substrate includes at least one leadframe having spaced apart regions of copper distributed across and extending from the surface into at least one layer of the multi-layer substrate. The method can also include forming nanotwin copper bond pads on the surface of the multi-layer substrate over a respective region of the regions of copper. The method can also include removing the mask and forming a layer of an insulating material over the surface of the multi-layer substrate and around the nanotwin copper bond pad.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

Die attach materials are provided. In one example, the die-attach material includes a plurality of core-shell particles. Each core-shell particle includes a core and a shell on the core. The core includes a conducting material. The shell includes a metal nitride.

A semiconductor package includes a metallic substrate, the metallic substrate including a roughened surface, a semiconductor die including bond pads, and an adhesive between the roughened surface of a topside of the metallic substrate and the semiconductor die, therein bonding the semiconductor die to the metallic substrate. The adhesive includes a resin. The metallic substrate further includes a groove about a perimeter of the semiconductor die on the roughened surface, the groove having a surface roughness less than a surface roughness of the roughened surface of the metallic substrate. The groove straddles the topside and a sidewall of the metallic substrate.

According to one embodiment, a semiconductor device includes a semiconductor element provided on a first surface of a lead frame; a package member provided on the lead frame and on the semiconductor element and having a first concave part; and a first terminal provided in the first concave part and extending in a first direction that is parallel to the first surface of the lead frame. The first concave part has a concave shape having a first length in the first direction, a second length in a second direction perpendicular to the first surface of the lead frame, and a third length in a third direction perpendicular to the first direction and the second direction. The third length is shorter than a length of the package member in the third direction.