A double-sided liquid-cooling power module mounted with a plurality of power semiconductor devices, including a watertight housing and a power device package, the power device package including a lower ceramic substrate, a power semiconductor device, a copper saddle-shaped upper guide column, an upper ceramic substrate, a shunt support column, and a resin dielectric package, a bottom surface electrode of the power semiconductor device being correspondingly press-bonded with a silver thin film layer, a top surface electrode being press-bonded with an interfacial silver thin film layer; the power semiconductor device is encapsulated by the resin dielectric package; an electrical conduction loop is formed by press-bonding the power semiconductor device to the lower ceramic substrate via the silver thin film layer and press-bonding the copper saddle-shaped upper column to the power semiconductor device via the silver thin film layer; a double-sided heat dissipation effect is achieved with the watertight housing.

Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.

A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

A package structure and a method for manufacturing the same, and an electronic device are provided. The package structure includes a substrate, a chip stack, a heat dissipation layer, and a molding layer. The chip stack is disposed on the substrate, the heat dissipation layer is disposed on the chip stack, and the molding layer is disposed on the substrate and covers the chip stack. The molding layer is in contact with the heat dissipation layer, the molding layer and the heat dissipation layer are coplanar, and the thermal conductivity coefficient of the plastic encapsulating layer is less than the thermal conductivity coefficient of the heat dissipation layer.

Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises a first substrate having first pads on a first surface of the first substrate, a second substrate on the first substrate and having a plurality of second pads on a second surface of the second substrate, and connection terminals between the first substrate and the second substrate and correspondingly coupling the first pad to the second pads. Each of the connection terminals has a first major axis and a first minor axis that are parallel to the first surface of the first substrate and are orthogonal to each other. When viewed in a plan view, the first minor axis of each of the connection terminals is directed toward a center of the first substrate.

A package structure includes a circuit substrate, a semiconductor package, a first ring structure and a second ring structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The first ring structure is attached to the circuit substrate and surrounding the semiconductor package, wherein the first ring structure includes a central opening and a plurality of corner openings extending out from corners of the central opening, the semiconductor package is located in the central opening, and the plurality of corner openings is surrounding corners of the semiconductor package.

In one example, an electronic device includes a substrate having a conductive structure, an electronic component coupled to the conductive structure at a first side of the substrate, wherein the electronic component includes a first side facing the first side of the substrate and a second side opposite the first side, vertical interconnects disposed around the electronic component, wherein the vertical interconnects are coupled to the conductive structure at the first side of the substrate, a thermal body coupled to the second side of the electronic component, an interposer coupled to the vertical interconnects, wherein the interposer includes inner sidewalls defining an opening disposed around the thermal body, and an encapsulant disposed between the thermal body and the inner sidewalls of the interposer, around the vertical interconnects, and around the electronic component, wherein the thermal body is exposed from the encapsulant. Other examples and related methods are also disclosed herein.

A semiconductor device includes a semiconductor element having a surface on which a first electrode and a second electrode are disposed, a conductor plate having a surface facing the surface of the semiconductor element and electrically connected to the first electrode, an insulating layer disposed on the surface of the conductor plate and covers a part of the surface of the conductor plate, and a conductor circuit pattern disposed on the insulating layer. The conductor circuit pattern has at least one conductor line electrically connected to the semiconductor element. The at least one conductor line includes a conductor line electrically connected to the second electrode.

A method for mounting a fin system in a power module includes: sintering a fin system to a first base substrate, the fin system comprising a plurality of fins attached to and extending away from a base plate; sintering a first power switch component to the first base substrate; sintering a second power switch component to a second base substrate; and soldering a heat dissipation element to the second base substrate.

The present disclosure relates to a power module. The power module includes a first substrate having a first surface and a second surface opposite to the first surface; a first die disposed on the first surface of the first substrate; and a second die disposed on the second surface of the first substrate, wherein at least one of the first die and the second die is a power die. A first thickness of the first die is different from a second thickness of the second die.