A semiconductor package includes a package substrate including a first chip mounting area, a second chip mounting area, and a third chip mounting area spaced apart from one another in a first direction, semiconductor chips mounted on the first to third chip mounting areas, a first stiffener mounted on the package substrate to separate the first chip mounting area from the second chip mounting area, and a second stiffener mounted on the package substrate to separate the second chip mounting area from the third chip mounting area.

A pixel device including a first floor including a first LED, a first lower pad, and a first upper pad electrically connected to the first LED; a second floor disposed over the first floor, and including a second LED, a second lower pad, and a second upper pad electrically connected to the second LED; and a third floor disposed over the second floor, and including a third LED, a third lower pad, and a third upper pad electrically connected to the third LED.

A double-sided cooling package for a double-sided, bi-directional junction transistor can include a double-sided, bi-directional, junction transistor chip with an individual, double-sided, bi-directional power switch (collectively, a DSTA). The DSTA can be sandwiched between heat sinks. Each heat sink can include a direct plating copper (DPC) structure, a direct copper bonding (DCB) structure or a direct aluminum bond (DAB) structure. In addition, each heat sink can have opposed first and second copper layers on a substrate, and copper contacts that extend from a respective second copper layer through vias in each substrate to an exterior of the cooling package.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die, the second and third dies having a first surface and an opposing second surface, the first surfaces of the second and third dies electrically coupled to the first die, and the third die including voltage regulator circuitry; a first material around the second and third dies, the first material having a non-planar surface; a second material, on the non-planar surface of the first material and the second surfaces of the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and a redistribution layer (RDL) on and coupled to the second material, the RDL including a conductive pathway electrically coupled to the second and third dies by interconnects.

One aspect of the present disclosure pertains to a package structure. The package structure includes a die bonded to a substrate, where a plurality of first channels are formed on a top surface of the die; a lid bonded to the substrate and over the die; and a thermal interface material (TIM) disposed between and contacting the lid and the die, where the thermal interface material fills the first channels.

A package structure includes a package substrate, a semiconductor module on the package substrate, a composite thermal interface material (TIM) layer including liquid metal in a polymer matrix on the semiconductor module, a package lid on the composite TIM layer and attached to the package substrate, and a reactive interface layer in contact with the composite TIM layer on at least one of the semiconductor module or the package lid.

Disclosed herein are chip packages having stiffeners and methods for making the same. In one example, a chip package includes a substrate, an integrated circuit (IC) die complex, a spacer, and a stiffener. The IC die complex is mechanically connected to the substrate. The spacer is formed on a top surface of the substrate outward of the IC die complex. The stiffener includes a ring base and a flange that extends inward from the ring base. The ring base has a bottom surface that is attached to the top surface of the substrate. The flange has a bottom surface attached to the top surface of the spacer. The attachment to the stiffener at inner and outer locations provides enhanced resistance to warpage.

A system includes: an inverter configured to convert DC power from a battery to AC power to drive a motor, wherein the inverter includes: a power module including: a first phase switch including one or more first phase power switches on a first side of a substrate; and a second phase switch including one or more second phase power switches on a second side of the substrate opposite to the first side.

A semiconductor package includes a substrate including a wiring; a chip stack including a plurality of semiconductor chips stacked on the substrate, wherein each of the plurality of semiconductor chips has upper and lower surfaces, opposite to each other, front and rear surfaces, opposite to each other, left and right surfaces, opposite to each other, and connection pads disposed on the upper surface adjacent to the front surface; bonding wires electrically connecting the connection pads to the wiring of the substrate; a plurality of attachment films disposed on the lower surface of each of the plurality of semiconductor chips; a mold layer covering the chip stack and the bonding wires; and connection bumps disposed below the substrate, and electrically connected to the wiring, wherein at least one of the plurality of attachment films covers the rear surface of at least one semiconductor chip among the plurality of semiconductor chips.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.