An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

In a described example, an apparatus includes: a package substrate with conductive leads; a semiconductor die mounted to the package substrate, the semiconductor die having a first thickness; electrical connections coupling bond pads on the semiconductor die to conductive leads on the package substrate; brackets attached to the package substrate spaced from the semiconductor die and extending away from the package substrate to a distance from the package substrate that is greater than the first thickness of the semiconductor die; and mold compound covering the package substrate, the semiconductor die, the brackets, and the semiconductor die to form a semiconductor device package having a board side surface and a top surface opposite the board side surface, and having portions of the brackets exposed from the mold compound on the top surface of the semiconductor device package to form mounts for a passive component.

A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

A semiconductor package includes: a support substrate; a first semiconductor chip on the support substrate, the first semiconductor chip including one or more first chip pads; a second semiconductor chip spaced apart from the first semiconductor chip, the second semiconductor chip including one or more second chip pads; a third semiconductor chip on the first semiconductor chip and the second semiconductor chip, the third semiconductor chip comprising one or more third chip pads; one or more first conductive structures on the one or more first chip pads; one or more second conductive structures on the one or more second chip pads; and a redistribution layer on the one or more first conductive structures, the one or more second conductive structures, and the one or more third chip pads.

A semiconductor package includes a package substrate, a first chip group including at least one first chip spaced apart from the package substrate in a first direction perpendicular to a surface of the package substrate, a second chip group including at least one second chip disposed between the package substrate and the first chip group, a first molding film that surrounds the first chip group, a second molding film that surrounds the second chip group, and an alignment post that penetrates the first molding film and contacts the second molding film. The second molding film covers a surface of an end portion of the alignment post facing the package substrate.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

A molded package includes: a semiconductor die; a substrate attached to a bottom side of the semiconductor die; an electrically conductive clip attached to a top side of the semiconductor die; and a mold compound encapsulating the semiconductor die. A top side of the electrically conductive clip faces away from the semiconductor die and has an exposed flat surface that overlays the semiconductor die and is not covered by the mold compound. A bottom side of the electrically conductive clip faces the semiconductor die and has a convex curved surface that is attached to the top side of the semiconductor die. Along a vertical cross-section of the electrically conductive clip from the exposed flat surface to the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the exposed flat surface and the convex curved surface. A method of producing the molded package is also described.

A package includes a memory stack attached to a logic device, the memory stack including first memory structures, a first redistribution layer over and electrically connected to the first memory structures, second memory structures on the first redistribution layer, a second redistribution layer over and electrically connected to the second memory structures, and first metal pillars on the first redistribution layer and adjacent the second memory structures, the first metal pillars electrically connecting the first redistribution layer and the second redistribution layer, wherein each first memory structure of the first memory structures includes a memory die comprising first contact pads and a peripheral circuitry die comprising second contact pads, wherein the first contact pads of the memory die are bonded to the second contact pads of the peripheral circuitry die.

Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.

A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.