A semiconductor device includes a transistor layer including a semiconductor substrate and gate structures on an upper surface of the semiconductor substrate, an upper substrate on the transistor layer, an upper wiring layer disposed between the transistor layer and the upper substrate and including upper conductive lines, a bonding layer between the upper wiring layer and the upper substrate, and a lower wiring layer disposed on a lower surface of the semiconductor substrate and including lower conductive lines. The transistor layer is disposed between the lower wiring layer and the upper wiring layer. The bonding layer includes a material having higher thermal conductivity than silicon oxide, and a dopant concentration of the upper substrate is lower than a dopant concentration of the semiconductor substrate.

A manufacturing method of a semiconductor device includes forming a semiconductor layer of a first conductivity type that is located on a substrate, simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench that runs through the semiconductor layer, simultaneously forming an insulator that fills up the first trench and an insulating layer that covers the second trench, removing a part of the insulator such that the bottom surface of the first trench is not exposed, removing a part of the insulating layer such that the semiconductor substrate is exposed in the second trench, embedding in the first trench a first conductor that is separated from the semiconductor layer, and embedding in the second trench a second conductor that is in contact with the semiconductor substrate. A width of the second trench is greater than a width of the first trench.

Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).

Methods, systems, and devices for power and signal distribution in stacked semiconductor systems are described. A semiconductor system may include a distribution component configured to communicate power, signals, or both with a logic component and memory component(s) of the semiconductor system. The distribution component may include power delivery circuitry to provide separate power to the memory component(s) and the logic component, data serialization/deserialization circuitry to communicate data signals with the logic component, or both. The distribution component may convey power, data signals, or both to the logic component using conductive vias that pass through the memory components and bypass interface circuitry of the memory component(s). The distribution component may include clock circuitry that receives, generates, or both, one or more clock signals and provides the one or more clock signals for I/O functionality of the distribution component, the logic component, the interface circuitry, or any combination thereof.

A semiconductor device including a semiconductor substrate, an interlayer insulation layer on the semiconductor substrate, a first via structure passing through the semiconductor substrate and the interlayer insulation layer and having a first diameter, and a second via structure passing through the semiconductor substrate and the interlayer insulation layer, the second via structure having a second diameter greater than the first diameter, at a same vertical level may be provided. A sidewall of the first via structure may include at least one undercut region horizontally protruding toward a center of the first via structure, and an outer sidewall of the second via structure may be in contact with either the semiconductor substrate or the interlayer insulation layer at an area above the undercut region.

A memory device includes a printed circuit board, a magnetoresistive random-access memory (MRAM) device coupled to the printed circuit board, a controller or control circuitry, wherein the controller or control circuitry is integrated into, embedded in, or otherwise incorporated into the MRAM device, and a field programmable gate array (FPGA) coupled to the printed circuit board and in communication with the controller or control circuitry.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, a non-conductive layer aligned with the semiconductor layer, and a contact structure in the non-conductive layer. The non-conductive layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

A semiconductor device includes first, second and third stacked chips with a first, second and third substrate, respectively, at least three first, second and third logical circuits, respectively, and at least two first, second and third vias, respectively, and a fourth chip stacked on the third chip having a fourth substrate, and at least three fourth logical circuits. First and second ones of the first to third logical circuits of the first to fourth chips are each configured to perform a first and second logical operation, respectively, on a first and second address input signal, respectively, received at the respective chip to thereby output a first and second address output signal, respectively. Third ones are each configured to activate the respective chip based on at least the second address output signal transmitted within the respective chip.

A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulating material.

A semiconductor device assembly can include a first semiconductor device comprising CMOS circuitry at a first active surface and a second semiconductor device having a footprint smaller than that of the first semiconductor device and including memory array circuitry at a second active surface hybrid-bonded to the first active surface. The assembly can further include a gapfill material directly contacting the first active surface of the first semiconductor device and having an upper surface coplanar with a back surface of the second semiconductor device, and a metallization layer disposed over the second semiconductor device and the gapfill material. The metallization layer can include conductive structures operably coupled to the second semiconductor device through back-side contacts of the second semiconductor device. The assembly can further include a plurality of bond pads disposed at an upper surface of the metallization layer and coupled to the conductive structures of the metallization layer.