A semiconductor package may include an interposer substrate having first and second surfaces, a through electrode extending through the interposer substrate, an RDL on the first surface of the interposer substrate and an upper surface of the through electrode and including a redistribution wiring structure, first and second semiconductor chips electrically connected to the redistribution wiring structure on the RDL, a first molding member on the RDL and covering sidewalls of the first and second semiconductor chips, a conductive post on the second surface of the interposer substrate and contacting the through electrode, and a second molding member on the second surface of the interposer substrate and covering a sidewall of the conductive post. A maximum width of the through electrode is equal to or greater than that of the conductive post. A length of the through electrode is equal to or less than that of the conductive post.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

A structure includes a first core substrate; an adhesive layer on the first core substrate; a second core substrate on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device within the first cavity; a first insulating film extending over the second core substrate, over a top surface of the first semiconductor device, and within the first cavity; a through via extending through the first insulating film, the first core substrate, and the second core substrate; a first routing structure on the first core substrate and electrically connected to the through via; and a second routing structure on the first insulating film and electrically connected to the through via and the first semiconductor device.

A method of making an interconnect substrate, comprising disposing an embedded component and at least one tracking identifier in a substrate core, and planarizing the substrate core to form a planar surface, forming a conductive layer over a frontside planar surface, disposing a layer of dielectric over the frontside planar surface, the embedded component, and the conductive layer, rotating the substrate core such that a back surface of the substrate core is configured for processing, and forming a conductive layer over the back surface of the substrate core.

Systems, devices, and methods for high die stack packages with modular structures are provided herein. A die stack package can include a substrate, a proximal unit carried by the substrate, and a distal unit carried by the proximal unit. The proximal unit can include first and second proximal die stacks, a proximal portion of a modular structure, and proximal wire bonds electrically coupling the first and second proximal die stacks to conducting elements of the modular structure. The distal unit can include first and second distal die stacks, a distal portion of the modular structure, and distal wire bonds electrically coupling the first and second distal die stacks to the conducting elements of the modular structure. In some embodiments, the die stack package further includes one or more modular units stacked between the proximal unit and the distal unit.

A substrate structure includes an insulating layer and a circuit structure disposed on an upper surface of the insulating layer. The upper surface of the insulating layer includes a chip placement region for placing a chip. The circuit structure includes a first circuit located outside the chip placement region and having a first conductive trace, and a second circuit located within the chip placement region and having a second conductive trace. A width of a region covered by the second circuit is greater than a width of the first circuit. Therefore, the width of the region covered by the circuit passing through the chip placement region is widened and is greater than the width of the circuit outside the chip placement region, thereby increasing the contact area between the chip and the circuit, and dispersing the reaction force from the circuit that the chip receives during hot pressing process.

A semiconductor device includes a semiconductor element, a sealing member, and a rewiring layer. The rewiring layer includes an insulating layer covering a front surface of the semiconductor element and a part of the sealing member, an electrode connected to the semiconductor element, and an externally-exposed layer being conductive and covering a portion of the electrode exposed from the insulating layer.

A semiconductor structure includes: a substrate; a package attached to a first surface of the substrate, where the package includes: an interposer, where a first side of the interposer is bonded to the first surface of the substrate through first conductive bumps; dies attached to a second side of the interposer opposing the first side; and a molding material on the second side of the interposer around the dies; a plurality of thermal interface material (TIM) films on a first surface of the package distal from the substrate, where each of the TIM films is disposed directly over at least one respective die of the dies; and a heat-dissipation lid attached to the first surface of the substrate, where the package and the plurality of TIM films are disposed in an enclosed space between the heat-dissipation lid and the substrate, where the heat-dissipation lid contacts the plurality of TIM films.

An electronic package is provided, in which an electronic module and at least one support member are disposed on a substrate structure having a circuit layer, such that the stress on the substrate structure is dispersed through the at least one support member to eliminate the problem of stress concentration and prevent the substrate structure from warping.

A semiconductor device includes: a substrate with a cell region and a chip guard region, the chip guard region surrounding the cell region; a first chip guard extending over the chip guard region in a first direction; a second chip guard extending over the chip guard region in the first direction, the second chip guard being spaced apart from the first chip guard; and a third chip guard extending over the chip guard region in a second direction, the second direction intersecting the first direction. The first chip guard includes a first end portion, the second chip guard includes a second end portion, and the third chip guard includes a third end portion that is disposed between the first end portion and the second end portion.