A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

A radio frequency (RF) chip package includes: an RF die; a first peripheral circuit chip; a second peripheral circuit chip; a substrate having a -shaped step formed on a portion thereof so that the RF die is mounted on top of the step of the substrate and the first peripheral circuit chip and the second peripheral circuit chip are mounted on top of the substrate where no step is formed; a first mutual inductance controller for controlling the dimension of the mutual inductance between the first peripheral circuit chip and the RF die; and a second mutual inductance controller for controlling the dimension of the mutual inductance between the second peripheral circuit chip and the RF die.

An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

A display device includes a first display substrate including a light emitting element layer, a second display substrate facing the first display substrate and including a light blocking member and a color conversion layer, a coupling member that connects the first display substrate and the second display substrate to each other, and a filling member disposed between the first display substrate and the second display substrate. The filling member includes a photoinitiator that initiates by absorbing light of a wavelength band in a range of about 380 nm to about 500 nm, and the light blocking member and the color conversion layer cover a side of an entire surface of the second display substrate.

A semiconductor package includes a redistribution substrate, a chip stack structure disposed on the redistribution substrate and including a plurality of semiconductor chips disposed in a stack, a vertical wiring portion connecting the chip stack structure to the redistribution substrate and including a plurality of vertical wires that extend in a direction perpendicular to an upper surface of the redistribution substrate, a sealing member configured to seal at least a portion the chip stack structure and the vertical wiring portion, and a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member.

Provided is a redistribution structure having reduced parasitic capacitance. The redistribution structure may include a via layer and a wiring layer disposed on the via layer in a first direction perpendicular to the via layer, the wiring layer including a metal plate and a first insulation pattern configured to penetrate the metal plate in the first direction. An outer side surface of the first insulation pattern may be exposed from a side surface of the metal plate.

An electronic device includes a first semiconductor component, a second semiconductor component, an encapsulation layer, and a circuit layer. The encapsulation layer has a first side, and the encapsulation layer surrounds the first semiconductor component and the second semiconductor component. The circuit layer is disposed on the first side of the encapsulation layer. The encapsulation layer has a first thickness, and the first semiconductor component has a second thickness. The first thickness is greater than the second thickness. A difference between the first thickness and the second thickness is greater than half of the first thickness and less than three times the second thickness. In a top view, the encapsulation layer has a first area, the first semiconductor component has a second area, the second semiconductor component has a third area, and a sum of the second area and the third area is greater than half of the first area.

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.