A non-contact semiconductor die singulation process utilizes compressed air to separate a first portion of a semiconductor wafer from a second portion of the semiconductor wafer. During the non-contact semiconductor die singulation process, the semiconductor wafer is placed on dicing tape. A channel is formed along various scribe lines in the semiconductor wafer. When the channels are formed, a compressed air tool applies compressed air along a length of the channel. Pressure from the compressed air causes the semiconductor wafer to deform. As the semiconductor wafer deforms, the semiconductor wafer cracks or splits along the length of the scribe line thereby separating the first portion of the semiconductor wafer from the second portion.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

A back-side ground and power-distribution network is formed on a semiconductor wafer substrate by selectively etching first and second back-side partial-substrate rail (PSR) trench openings through a back-side surface of the wafer substrate, selectively forming a plurality of defined n-type conductive regions and defined p-type conductive regions in the wafer substrate at the bottoms of the first and second back-side PSR trench openings in position for electrical contact with n-well and p-well regions, and then forming first and second back-side PSR conductors in the first and second back-side PSR trench openings to be directly electrically connected over the plurality of defined n-type conductive regions and defined p-type conductive regions to the n-well and p-well regions in the wafer substrate.

A backside power and ground distribution network is formed on a wafer substrate layer by selectively etching backside PSV openings through a backside surface of the wafer substrate layer, forming n-type and p-type conductive regions in the wafer substrate layer at the bottoms of first and second backside PSV openings in position for electrical contact with an n-well and p-well regions, and then forming first and second backside PSV conductors in the first and second backside PSV openings to be directly electrically connected over the n-type and p-type conductive regions to the n-well and p-well regions in the wafer substrate layer.

A method of manufacturing a semiconductor device is described. The method includes providing a parent substrate including a substrate portion of a first conductivity type. The method further includes forming an absorption layer in the parent substrate by an ion implantation process of an element through a first surface of the parent substrate. The method further includes forming a semiconductor layer structure on the first surface of the parent substrate. The method further includes splitting the parent substrate along a splitting section through a detachment layer. The detachment layer is arranged between the absorption layer and a second surface of the parent substrate at a vertical distance to the absorption layer.

A method of manufacturing a semiconductor device is described. The method includes providing a parent substrate including a substrate portion of a first conductivity type. The method further includes forming an absorption layer in the parent substrate by an ion implantation process of an element through a first surface of the parent substrate. The method further includes forming a semiconductor layer structure on the first surface of the parent substrate. The method further includes splitting the parent substrate along a splitting section through a detachment layer. The detachment layer is arranged between the absorption layer and a second surface of the parent substrate at a vertical distance to the absorption layer.

A semiconductor device including: a first level including a plurality of first metal layers; a second level overlaying the first level, where the second level includes at least one single-crystal silicon layer and a plurality of transistors, where each of the plurality of transistors includes a single-crystal channel, where the second level includes a plurality of second metal layers which includes interconnections between the plurality of transistors, the second level is overlaid by an isolation layer; a connective path from the plurality of transistors to the plurality of first metal layers, where at least one of the plurality of transistors includes a second single-crystal channel overlaying a first single-crystal channel, where each of at least one of the plurality of transistors includes at least a two sided gate, where the first single-crystal channel is self-aligned to the second single-crystal channel being processed following a same lithography step.

A manufacturing method of a chip-attached substrate includes preparing a stacked substrate including multiple chips, a first substrate to which the multiple chips are temporarily bonded, and a second substrate bonded to the first substrate with the multiple chips therebetween; and separating the multiple chips bonded to the first substrate and the second substrate from the first substrate to bond the multiple chips to one surface of a third substrate including a device layer.

A manufacturing method of a chip-attached substrate includes preparing a stacked substrate including multiple chips, a first substrate to which the multiple chips are temporarily bonded, and a second substrate bonded to the first substrate with the multiple chips therebetween; and separating the multiple chips bonded to the first substrate and the second substrate from the first substrate to bond the multiple chips to one surface of a third substrate including a device layer.

A method includes forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, heating respective top surfaces of the first mask line and the second mask line with polarized light, and forming a second masking layer over the first masking layer with an area selective deposition process. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.