A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

A semiconductor package contains a first semiconductor die, electrically coupled to a plurality of leads around a perimeter of the semiconductor package via a molded interconnect. The molded interconnect comprises a plurality of embedded interconnects in a first mold compound which electrically couple the plurality of bond pads of the first semiconductor die to the plurality of leads of the semiconductor package. The molded interconnect may have a greater cross-sectional area at a given pitch compared to a similar wire bonded semiconductor package and allow advantageous thermal management of the semiconductor package compared to other electrical coupling techniques. The molded interconnect may allow small high-power integrated circuits to be packaged with a package footprint which is smaller than would otherwise be available.

A semiconductor device, including: a semiconductor chip including an electrode on an upper surface thereof; and a wiring member including a bonding portion, a rising portion, and a connecting portion, the bonding portion being bonded to the electrode via a bonding material, the rising portion being of a shape of a flat plate and extending upward from the bonding portion, the connecting portion connecting the bonding portion to the rising portion. The rising portion includes a lower region connected to the connecting portion and an upper region located above the lower region. Both the lower region and the connecting portion have a first thickness, and the upper region has a second thickness that is larger than the first thickness.

In examples, a semiconductor package comprises a semiconductor die having a device side including circuitry and a non-device side opposing the device side. The semiconductor package comprises a polyimide substrate coupled to the non-device side of the semiconductor die by an adhesive layer. The semiconductor package comprises a conductive terminal coupled to the polyimide substrate by the adhesive layer, and a bond wire coupled to the device side of the semiconductor die and to the conductive terminal. The semiconductor package comprises a mold compound covering the semiconductor die, the polyimide substrate, the bond wire, and at least part of the conductive terminal, with the conductive terminal extending to an exterior of the mold compound.

A semiconductor module includes: a board that includes a wiring portion formed on at least one surface and a hole portion having an opening on the at least one surface side; and a body portion that is disposed on one surface side of the board and is sealed by a resin, and a lead portion having a plate shape that extends toward an outside from a side surface of the body portion. In at least one semiconductor package, a part of the body portion is inserted into the hole portion, and the lead portion extends along a surface of the board, and a lower surface of the lead portion is bonded to the wiring portion.

A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a protective element, and a sensor device. The protective element encapsulates the carrier. The sensor device is embedded in the carrier and the protective element. The sensor device includes a sensing portion and a protective portion adjacent to the sensing portion, and the protective portion of the sensor device has a first surface exposed from the protective element and the carrier.

A method for manufacturing a power device fabrication panel includes aligning a first alignment mark in a lead frame of a power device substrate array with a second alignment mark in a bonding fixture. The power device substrate array includes a plurality of power device pockets, the bonding fixture includes a plurality of power device openings, and the power device openings are in assembly alignment with the power device pockets when the first alignment mark is aligned with the second alignment mark. And with the bonding fixture power device openings in assembly alignment with the power device pockets of the power device substrate array, a plurality of power devices are moved at least partially through the aligned power device openings and into the power device pockets where they are bonded.

A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

An electronic device may include an electrically conductive base, an electrically insulative layer attached to the base, and first and second exterior terminals at an exterior surface. A first electrical conductor may be attached to the electrically insulative layer and electrically connected to the first exterior terminal. A semiconductor die may have a first contact at a bottom surface electrically connected to the first electrical conductor, and a second contact at a top surface. A second electrical conductor may be attached to the top surface of the semiconductor die and may be electrically connected to the second exterior terminal. An encapsulant may at least partially encapsulate the electrically conductive base, the first and second exterior terminals, the electrically insulative layer, the first electrical conductor, the semiconductor die, and the second electrical conductor.