A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A temporary fixing composition contains an organic component in a proportion of 42 mass % or more and 95 mass % or less. The organic component is solid at 25 C. and has a 95% mass loss temperature in nitrogen of 300 C. or lower. The temporary fixing composition is used to temporarily fix a first bonding target material and a second bonding target material to each other before the two bonding target materials are bonded to each other. A method for producing a bonded structure of the present invention includes temporarily fixing a first bonding target material and a second bonding target material to each other with the temporary fixing composition disposed therebetween and firing the temporarily fixed two bonding target materials to bond the two bonding target materials to each other.

A die attach film structure includes a dicing film, an insulating adhesion layer including an upper surface and a lower surface opposite the upper surface, the lower surface of the insulating adhesion layer contacting an upper surface of the dicing film and including an insulating filler, and a conductive adhesion layer contacting an upper surface of the insulating adhesion layer and including a conductive filler.

A semiconductor package comprises a base chip, a plurality of semiconductor chips sequentially stacked on the base chip, bump structures between the base chip and a lowermost semiconductor chip of the plurality of semiconductor chips, and between the plurality of semiconductor chips, adhesive layers surrounding the bump structures between the base chip and the lowermost semiconductor chip of the plurality of semiconductor chips and between the plurality of semiconductor chips. The adhesive layers have a width equal to or less than a width of each of the plurality of semiconductor chips in a direction parallel to an upper surface of the base chip. At least one of the adhesive layers comprises a polymer resin having a hydrophilic group, a photosensitive compound physically bonded to the polymer resin, and an ionic material crosslinking the polymer resin.

A method of manufacturing a semiconductor package includes the following steps. A first integrated circuit is encapsulated by a first encapsulant. A first passivation layer is formed over the first integrated circuit and the first encapsulant. A first thermal pattern is formed in the first passivation layer. A second passivation layer is formed on the first passivation layer and the first thermal pattern, wherein the first thermal pattern is exposed by a first opening of the second passivation layer. A second integrated circuit is adhered to the second passivation layer through an adhesive layer, wherein the adhesive layer is partially disposed in the first opening of the second passivation layer.

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Provided is a thermosetting resin composition containing: (A) silver particles including secondary particles having an average particle size from 0.5 to 5.0 m, the secondary particles being formed by aggregation of primary particles having an average particle size from 10 to 100 nm; and (B) a thermosetting resin.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface. The first redistribution structure includes a first pad and a second pad, the first pad is adjacent to the first surface, and the second pad is adjacent to and exposed from the second surface. The chip package structure includes a chip package bonded to the first pad through a first bump, wherein a first width of the first pad decreases in a first direction away from the chip package, and a second width of the second pad decreases in the first direction. The chip package structure includes a second bump over the second pad.

An electronic device includes a non-conductive die attach film on a side of a conductive lead, a semiconductor die having a first side and a lateral side, the first side on the non-conductive die attach film, and the lateral side including striations, and a package structure enclosing the semiconductor die and a portion of the conductive lead. A method includes singulating portions of a non-conductive die attach film on a carrier, attaching a backside of a wafer to the singulated portions of the non-conductive die attach film, and singulating semiconductor dies of the wafer while the backside of the wafer is attached to the singulated portions of the non-conductive die attach film.