A semiconductor package includes a package substrate; a semiconductor die vertically stacked on the package substrate; a redistribution layer (RDL) including a dielectric material and metal features that electrically connect the semiconductor die to the package substrate, the RDL having a first Young's modulus; a first underfill layer disposed between the RDL and the semiconductor die; and stress buffers embedded in the RDL below corners of the semiconductor die, each stress buffer having a second Youngs modulus that is at least 30% less than the first Youngs modulus.

An embodiment relates to a compound including: an indene ring; a vinylbenzyl group; and an aromatic ring-containing group of 6 or more carbon atoms without a polymerizable carbon-carbon double bond, in which both of the vinylbenzyl group and the aromatic ring-containing group are directly bonded to the indene ring.

A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.

A package is formed that encapsulates first and second components having respective first and second thickness differing from each other. Each component has lower surface provided with electrical contact pads and an upper surface opposite the lower surface. A volume of molding material encapsulates the first component. The package includes a set redistribution layers including a set of electrically-conductive interconnects surrounded by electrically-insulating material. The redistribution layers are disposed above the upper surface of the first component. The package includes one or more electrically conductive interconnects that pass through the redistribution layers to the lower surface of the first component; The second component is disposes at a location adjacent to the first component. A first portion of the second component is surrounded by the volume of molding material and a second portion of the second component is surrounded by one or more of the redistribution layers.

An embodiment is a device including an integrated circuit die having an active side and a back side, the back side being opposite the active side, a molding compound encapsulating the integrated circuit die, and a first redistribution structure overlying the integrated circuit die and the molding compound, the first redistribution structure including a first metallization pattern and a first dielectric layer, the first metallization pattern being electrically coupled to the active side of the integrated circuit die, at least a portion of the first metallization pattern forming an inductor.

Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate. In an embodiment, a portion of the first substrate extends past edge surfaces of the second substrate and the third substrate. In an embodiment, a layer surrounds the portion of the first substrate, where the layer comprises a tapered cross-sectional shape, and where a first sidewall that contacts the second substrate and the third substrate has a first height that is greater than a second height of a second sidewall that faces away from the second substrate and the third substrate.

Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.

Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.

Embodiments disclosed herein may include an apparatus that includes a substrate with a first edge surface. In an embodiment, the substrate may comprise a glass layer. In an embodiment, a via is formed through a thickness of the substrate. In an embodiment, an organic dielectric layer is provided over the substrate, and the organic dielectric layer has a second edge surface. In an embodiment, a recess is formed into the second edge surface of the organic dielectric layer.

An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.