Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.

3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.

A substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. The core layer may include a glass material weaved throughout the core to provide stabilization and avoid warpage. A metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

A substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. The core layer may include a glass material weaved throughout the core to provide stabilization and avoid warpage. A metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

Disclosed herein are chip packages and methods for fabricating and operating the same. In one example, a chip package is provided that includes a first die stack having a first side mounted to a first interposer, a first I/O die having a first side mounted to the first interposer, and a first compute die complex mounted on a second side of the first die stack. The first compute die complex including at least a first compute die having functional circuitry coupled to circuitry of the first I/O die through vias extending through the first die stack.

A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.

Electrical circuitry is produced on the surface of an organic polymer. The electrical circuitry is produced on a support, and a polymerizable composition is brought into contact with the support and the circuitry. The polymerizable composition is polymerized while in contact with support and the circuitry to produce a solid, organic polymer. The electrical circuitry becomes adhered to and partially embedded in a surface of the solid organic polymer. The support may be removed subsequent to the polymerization step to expose the circuitry at the surface of the solid organic polymer.

Electrical circuitry is produced on the surface of an organic polymer. The electrical circuitry is produced on a support, and a polymerizable composition is brought into contact with the support and the circuitry. The polymerizable composition is polymerized while in contact with support and the circuitry to produce a solid, organic polymer. The electrical circuitry becomes adhered to and partially embedded in a surface of the solid organic polymer. The support may be removed subsequent to the polymerization step to expose the circuitry at the surface of the solid organic polymer.

A semiconductor package includes a redistribution layer, a first substrate disposed on the redistribution layer and having a first cavity, a first semiconductor chip in the first cavity and having a first connection pad, a first encapsulant covering the first semiconductor chip and filling the first cavity, a second substrate disposed on the first substrate and having a second cavity, a second semiconductor chip in the second cavity and having a second connection pad, a second encapsulant covering the second semiconductor chip and filling the second cavity, a first connection via penetrating through the first encapsulant, directly connected to the first connection pad, and connecting the first connection pad to the redistribution layer, and a second connection via penetrating through the first substrate and the first and second encapsulants, directly connected to the second connection pad, and connecting the second connection pad to the redistribution layer.

A package structure and a formation method of a package structure are provided. The method includes forming a semiconductor interposer and bonding a chip-containing structure to the semiconductor interposer. The method also includes bonding a memory-containing structure to the semiconductor interposer. The method further includes bonding the semiconductor interposer to a redistribution interposer after the chip-containing structure and the memory-containing structure are bonded to the semiconductor interposer. The redistribution interposer has multiple organic layers.