The present invention provides a reduced-height image-capturing module, which includes a lens assembly, an image-sensing chip, a carrier base and a circuit substrate. The carrier base has a base body, two extending plate bodies extending and a base groove recessed. A lower portion of the base body enters a through opening of the circuit substrate, and the two extending plate bodies cross over the through opening of the circuit substrate and are disposed on an upper surface of the circuit substrate. The image-sensing chip is disposed on a recessed bottom surface of the base groove which is not at the same level as the upper surface of the circuit substrate, so that the recessed bottom surface is lower than the upper surface of the circuit substrate. The lens assembly is disposed on the upper portion of the base body and corresponds to the image-sensing chip.

The present invention provides a reduced-height image-capturing module, which includes a lens assembly, an image-sensing chip, a carrier base and a circuit substrate. The carrier base has a base body, two extending plate bodies extending and a base groove recessed. A lower portion of the base body enters a through opening of the circuit substrate, and the two extending plate bodies cross over the through opening of the circuit substrate and are disposed on an upper surface of the circuit substrate. The image-sensing chip is disposed on a recessed bottom surface of the base groove which is not at the same level as the upper surface of the circuit substrate, so that the recessed bottom surface is lower than the upper surface of the circuit substrate. The lens assembly is disposed on the upper portion of the base body and corresponds to the image-sensing chip.

A method comprises: covering at least part of the integrated circuit with a material, the material including an opening that penetrates through the material; and forming a layer of nanoparticles on at least part of an internal wall of the opening and over at least part of the integrated circuit.

A semiconductor device having a fan-out package structure includes a semiconductor element having a first electrode pad and a second electrode pad on a front surface, a sealing material covering a side surface of the semiconductor element and a redistribution layer covering the front surface of the semiconductor element and a part of the sealing material. The redistribution layer includes an insulation layer, a first redistribution wire and a second redistribution wire. At least a part of the first redistribution layer is disposed above a boundary between the side surface of the semiconductor element and the sealing material. The second redistribution wire is electrically connected to the second electrode pad, and at least has a part that extends to a position outside of a contour of the semiconductor element over the first redistribution wire. The second redistribution wire is electrically independent of the first redistribution wire.

The package-on-package (POP) structure includes a first package unit of three-dimensional fan-out memory chips and a SiP package unit of the two-dimensional fan-out peripheral circuit chip. The first package unit includes: memory chips laminated in a stepped configuration; a molded substrate; wire bonding structures; a first rewiring layer; a first encapsulating layer; and first metal bumps, formed on the first rewiring layer. The SiP package unit includes: a second rewiring layer; a peripheral circuit chip; a third rewiring layer, bonded to the circuit chip; first metal connection pillars; a second encapsulating layer for the circuit chip and the first metal connection pillars; and second metal bumps on the second rewiring layer. The first metal bumps are bonded to the third rewiring layer. Integrating the two package units into the POP is enabled by three rewiring layers and the molded substrate which supports the first package unit during wire bonding process.

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

An example ceramic panel has a first surface and a second surface. The ceramic panel has a bond finger well on the first surface of the ceramic panel a scribe line well on the second surface of the ceramic panel. The ceramic panel also has a scribe line along the scribe line well.

A semiconductor device includes a substrate, a circuit layer, a dielectric layer, a trace layer, a metal buffer layer, and a metal wire bonding pad. The circuit layer is on an upper surface of the substrate. The dielectric layer is on an upper surface of the circuit layer. The trace layer is on an upper surface of the circuit layer and in the dielectric layer. The metal buffer layer is on an upper surface of the trace layer and in the dielectric layer. The metal wire bonding pad is on an upper surface of the metal buffer layer.

A semiconductor package includes a package substrate, first and second semiconductor chips stacked on the package substrate and wire-bonded to the package substrate. The first semiconductor chip includes first differential pair signal pads, a first option signal pad, and a first signal path control circuit. The second semiconductor chip includes second differential pair signal pads, a second option signal pad, and a second signal path control circuit. The first signal path control circuit changes a signal path of one of the differential pair signals of the first semiconductor chip by a first control signal. The second signal path control circuit changes a signal path of one of the differential pair signals of the second semiconductor chip by a second control signal.

An assembly comprising a substrate with a first and second bond pad at a top surface; and a semiconductor die with a lower surface coupled to the top surface, an upper surface with a third and fourth bond pad thereat, and a side surface perpendicular to the upper and lower surfaces. The first bond pad can be a first distance, the second bond pad can be a second distance, the third bond pad can be a third distance, and the fourth bond pad can be a fourth distance, respectively, from the side surface. The first and third distances summed can be the same as the second and fourth distances summed. A first wire can extend between the first and third bond pads, and a second wire can extend between the second and fourth bond pads.