In examples, a semiconductor package comprises a semiconductor die having a device side including circuitry and a non-device side opposing the device side. The semiconductor package comprises a polyimide substrate coupled to the non-device side of the semiconductor die by an adhesive layer. The semiconductor package comprises a conductive terminal coupled to the polyimide substrate by the adhesive layer, and a bond wire coupled to the device side of the semiconductor die and to the conductive terminal. The semiconductor package comprises a mold compound covering the semiconductor die, the polyimide substrate, the bond wire, and at least part of the conductive terminal, with the conductive terminal extending to an exterior of the mold compound.

A semiconductor device includes semiconductor elements. Each semiconductor element, including first, second and third electrodes, is controlled to turn on and off current flow between the first electrode and the second electrode by drive signals inputted to the third electrode. The first electrodes of the semiconductor elements are electrically connected mutually, and the second electrodes of the semiconductor elements are electrically connected mutually. The semiconductor device further includes a control terminal receiving the drive signals, a first wiring section connected to the control terminal, a second wiring section, and third wiring sections, and further a first connecting member electrically connecting the first and the second wiring sections, a second connecting member electrically connecting the second wiring section and each third wiring section, and third connecting members connecting the third wiring sections and the third electrodes of the semiconductor elements.

The present disclosure provides a semiconductor structure, comprising a die/die stack attached on a substrate, a conductive top block covering a top surface of the die/die stack, and a plurality of ground wires conductively connect the conductive top block and to the substrate. The conductive top block, the plurality of ground wires, and the substrate form a Faraday cage to provide an electromagnetic interference shielding of the die/die stack.

A variety of footed and leadless semiconductor packages, with either exposed or isolated die pads, are described. Some of the packages have leads with highly coplanar feet that protrude from a plastic body, facilitating mounting the packages on printed circuit boards using wave-soldering techniques.

An electronic package is provided, in which an electronic element is disposed on a carrier structure, and an interposer is stacked on the electronic element. Further, a wire is connected to the interposer and grounds the carrier structure, such that the wire and the interposer surround the electronic element. Therefore, the wire can be used as a shielding element when the electronic package is in operation to prevent the electronic element from being subjected to external electromagnetic interference.

There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a Cu core material), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at %.

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method.

An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.

In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.

A described example includes a method for fabricating an integrated circuit (IC) device. The method can include forming a mask on a surface of a multi-layer substrate, in which the multi-layer substrate includes at least one leadframe having spaced apart regions of copper distributed across and extending from the surface into at least one layer of the multi-layer substrate. The method can also include forming nanotwin copper bond pads on the surface of the multi-layer substrate over a respective region of the regions of copper. The method can also include removing the mask and forming a layer of an insulating material over the surface of the multi-layer substrate and around the nanotwin copper bond pad.