Various embodiments of fanout packages are disclosed. A method of forming a microelectronic assembly is disclosed. The method can include bonding a first surface of at least one microelectronic substrate to a surface of a carrier using a direct bonding technique without an intervening adhesive, the microelectronic substrate having a plurality of conductive interconnections on at least one surface of the microelectronic substrate. The method can include applying a molding material to an area of the surface of the carrier surrounding the microelectronic substrate to form a reconstituted substrate. The method can include processing the microelectronic substrate. The method can include singulating the reconstituted substrate at the area of the surface of the carrier and at the molding material to form the microelectronic assembly.

A component forming machine with jammed component mitigation. In some examples, the component forming machine can include a platform configured to receive a lower die that supports a plurality of components for forming and includes a void through which at least some of the plurality of components pass subsequent to the forming, a die press positioned above the lower die and configured to lower an upper die to exert downward pressure on the plurality of components to form unformed components and formed components, and a separation system. In some examples, the separation system is configured to interact with the lower die to permit the formed components to fall into the void and prevent the unformed components from falling into the void.

A semiconductor die includes semiconductor devices located on a semiconductor substrate, metal-insulator-metal corner structures overlying the semiconductor devices and located in corner regions of the semiconductor die. Metal-insulator-metal corner structures are located in the corner regions of the semiconductor die. Each of the metal-insulator-metal corner structures has a horizontal cross-sectional shape selected from a triangular shape and a polygonal shape including a pair of laterally-extending strips extending along two horizontal directions that are perpendicular to each other and connected to each other by a connecting shape.

An electronic device includes a substrate, a through hole, a first electronic unit, a second electronic unit, a circuit structure, and a third electronic unit. The substrate has a first surface, a second surface opposite the first surface, a first cavity, and a second cavity. A sidewall of the first cavity is connected to the first surface, and a sidewall of the second cavity is connected to the first surface. The through hole extends through the substrate, and a sidewall of the through hole is connected to the first surface and the second surface. The first electronic unit is disposed in the first cavity. The second electronic unit is disposed in the second cavity. The circuit structure is disposed on the first electronic unit and the second electronic unit. The bottom surfaces of the first and second cavities have a roughness ranging from 0 to 2 micrometers.

A method of manufacturing a semiconductor package includes disposing a substrate strip having a plurality of semiconductor chips in a bottom mold, the bottom mold including sets of injection holes arranged on one side of the substrate strip, coupling the bottom mold and a top mold to contact each other, the top mold including cavities open toward corresponding ones of the sets of injection holes, individually injecting a first molding material and a second molding material into each of the cavities through injection holes included in a corresponding one of the sets of injection holes, respectively, forming a molding compound including the first molding material and the second molding material in the cavities, separating the top mold and the bottom mold from each other, curing the molding compound covering the semiconductor chips to form a mold structure, and cutting the mold structure.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

A bonded structure can include a first reconstituted element comprising a first element and having a first side comprising a first bonding surface and a second side opposite the first side. The first reconstituted element can comprise a first protective material disposed about a first sidewall surface of the first element. The bonded structure can comprise a second reconstituted element comprising a second element and having a first side comprising a second bonding surface and a second side opposite the first side. The first reconstituted element can comprise a second protective material disposed about a second sidewall surface of the second element. The second bonding surface of the first side of the second reconstituted element can be directly bonded to the first bonding surface of the first side of the first reconstituted element without an intervening adhesive along a bonding interface.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A packaging structure and a formation method thereof are provided. The packaging structure includes a carrier board, and a plurality of semiconductor chips adhered to the carrier board. Each semiconductor chip has a functional surface and a non-functional surface opposite to the functional surface, and a plurality of pads are formed on the functional surface of a semiconductor chip of the plurality of chips. A metal bump is formed on a surface of a pad of the plurality of pads, and a first encapsulation layer is formed on the functional surface. The packaging structure also includes a second encapsulation layer formed over the carrier board.

Semiconductor (SC) chip devices and associated methods of making are presented. The SC chips are designed to include enlarged extension semiconductor areas next to functional integrated circuit (IC) dies on these SC chips. Some variations include designing semiconductor wafers prior to fabrication so that the resultant IC dies are surrounded by the extension semiconductor areas. Other variations include processing post manufactured semiconductor wafers to expand the size of the available extension areas by including truncated pieces of IC dies that are immediately adjacent to functional working primary IC dies. These variations provide additional room for redistribution layers to fan-out from the IC dies outwards onto the extension areas.