A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.

An electronic device and a method of manufacturing an electronic device are provided. The electronic device includes a first conductive layer and a first power die. The first conductive layer including a first part and a second part separated from the first part. The first power die is disposed above the first conductive layer and has a first surface. The first power die includes a first terminal exposed from the first surface and a second terminal exposed from the first surface. The first part is electrically connected to the first terminal and the second part is electrically connected to the second terminal.

A semiconductor device including a capacitive HV isolation component and a method of fabrication thereof is disclosed. In one example, the semiconductor device comprises a semiconductor substrate, a bottom capacitor plate over the semiconductor substrate, a top capacitor plate over the bottom capacitor plate, and one or more conductive posts extending between the bottom plate and the top plate.

In one example, an electronic device, comprises a substrate comprising a first side and a second side opposite to the first side, wherein the substrate comprises dimples on the first side of the substrate, an electronic component over the first side of the substrate, an encapsulant over the first side of the substrate and covering a lateral side of the electronic component, and a first interconnect in the encapsulant and coupled to the electronic component and the substrate. Other examples and related methods are also disclosed herein.

A semiconductor package includes a package substrate having connection terminals. The connection terminals include first to fourth DQ terminals, and first and second CA terminals. A first chip stack has a first semiconductor chip flip-chip-mounted and connected to the first DQ terminals, and a fourth semiconductor chip on the first semiconductor chip wire-bonded to be connected to the fourth DQ terminals. A second chip stack has a second semiconductor chip flip-chip-mounted and connected to the second DQ terminals, and a third semiconductor chip on the second semiconductor chip wire-bonded and connected to the third DQ terminals. The first and third semiconductor chips are commonly connected to the first CA terminals, and the second and the fourth semiconductor chips are commonly connected to the second CA terminals.

Disclosed are embodiments of a semiconductor package. The semiconductor package may include: a first substrate; a chip stack on the first substrate, wherein the chip stack comprises one or more semiconductor chips that are stacked to be inclined at a first angle relative to a top surface of the first substrate; a tilt support structure, wherein the tilt support structure is between a first portion of the chip stack and the first substrate; and an anti-slip structure in contact with an end portion of the chip stack.

A semiconductor package may include a package substrate; first semiconductor chips sequentially stacked on an upper surface of the package substrate; a second semiconductor chip on an uppermost first semiconductor chip among the first semiconductor chips, the second semiconductor chip having an overhang region protruding from one side of the uppermost first semiconductor chip and an overlapping region overlapping the uppermost first semiconductor chip, the second chip pads including first bonding pads in the overhang region and second bonding pads in the overlapping region; first conductive bumps respectively on the first bonding pads; second conductive bumps respectively on the second bonding pads; vertical wires extending from the first conductive bumps to substrate pads of the package substrate, respectively; and a molding member covering the first semiconductor chips, the second semiconductor chip, and the vertical wires.

A semiconductor arrangement includes first and second semiconductor packages separate from one another. Each semiconductor package includes a die carrier having opposite first and second main faces, a transistor die disposed on the first main face, a first lead connected to a first load electrode of the transistor die, a second lead connected to a gate electrode of the transistor die, and an encapsulant embedding at least part of the first main face of the die carrier, inner portions of the leads and the transistor die. The first lead of the first semiconductor package is electrically connected to the first lead of the second semiconductor package, forming a source-source connection. The second lead of the first semiconductor package and the second lead of the second semiconductor package are arranged between the first semiconductor package and the second semiconductor package.

A semiconductor arrangement includes a substrate including a substrate metallization having line sections which are arranged so as to be electrically insulated from one another. A semiconductor element is connected to a first line section of the substrate metallization and has a contact surface on a side facing away from the substrate. A wiring element connects the contact surface of the semiconductor element to the substrate. The wiring element includes a first connecting section connecting the contact surface to a second line section of the substrate metallization, and a second connecting section connects the contact surface to a third line section of the substrate metallization, with the second line section and the third line section of the substrate metallization being designed such that the first connecting section and the second connecting section have an asymmetrical current flow during operation of the semiconductor arrangement.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.