In a described example, an apparatus includes: a metal leadframe including a dielectric die support formed in a central portion of the leadframe, and having metal leads extending from the central portion, portions of the metal leads extending into the central portion contacted by the dielectric die support; die attach material over the dielectric die support; a semiconductor die mounted to the dielectric die support by the die attach material, the semiconductor die having bond pads on a device side surface facing away from the dielectric die support; electrical connections extending from the bond pads to metal leads of the leadframe; and mold compound covering the semiconductor die, the electrical connections, the dielectric die support, and portions of the metal leads, the mold compound forming a package body.

A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.

Disclosed is a semiconductor package device comprising a lower redistribution substrate, a first semiconductor chip on the lower redistribution substrate, vertical structures on the lower redistribution substrate, and a first molding member on the lower redistribution substrate and on the first semiconductor chip and the vertical structures. The vertical structure includes a first post having a first diameter, a second post on the first post and having a second diameter, and a bonding pad on the second post opposite the first post and having a third diameter. The first, second, and third diameters are different from each other. The third diameter is greater than the second diameter.

A package substrate and a semiconductor package including the same are provided. The semiconductor package includes a package substrate including a base having a front side and a back side, rear pads below the back side of the base, lower connection patterns below the rear pads and in contact with the rear pads, first and second front pads on the front side of the base, a first support pattern on the front side of the base having a thickness greater than a thickness of each of the first and second front pads, and a protective insulating layer on the front side of the base and having openings exposing the first and second front pads respectively, and on an upper surface and a side surface of the first support pattern; a lower semiconductor chip on the protective insulating layer of the package substrate, spaced apart from the first support pattern in a horizontal direction; and a first upper semiconductor chip on the package substrate vertically overlapping the lower semiconductor chip and the first support pattern.

A semiconductor module includes a laminate substrate including a first circuit board on which a semiconductor device having a plurality of upper surface electrodes including a main electrode is disposed and a second circuit board, a main terminal electrically connected to the main electrode, an auxiliary terminal electrically connected to the one of the upper surface electrodes, and a main current wiring member electrically connecting the main electrode to the main terminal. A first path through which a first control current flows and a second path through which a second control current flows are provided between the one of the plurality of upper surface electrodes and the auxiliary terminal. The first control current flows via a first auxiliary wiring, and the second control current flows via the main current wiring member, the second circuit board and a second auxiliary wiring in this order.

A semiconductor package structure is provided. The semiconductor package structure includes a semiconductor die, a package substrate, and at least one bonding wire. The package substrate includes a dam structure to define a space where the semiconductor die is placed. The bonding wire is electrically connected between the semiconductor die and the package substrate.

A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package may include a first substrate, semiconductor dies stacked on the first substrate in a direction perpendicular to a top surface of the first substrate to have a stepwise structure, a mold layer disposed on the first substrate to cover the semiconductor dies, a second substrate disposed on the mold layer, and vertical conductive lines electrically connecting the semiconductor dies to the second substrate. The first substrate may include a first region and a second region. The first region may have a first thermal expansion coefficient, and the second region may have a second thermal expansion coefficient. The first thermal expansion coefficient may be different from the second thermal expansion coefficient.

A semiconductor package includes: a substrate; four semiconductor chips spaced apart from each other on the substrate, each of the four semiconductor chips including an active surface that is perpendicular to an upper surface of the substrate; wires extending from the active surface of each of the four semiconductor chips, respectively, and electrically connecting the four semiconductor chips and the substrate; and an encapsulant on the substrate and surrounding the four semiconductor chips, wherein upper surfaces and first side surfaces of each of the four semiconductor chips are exposed from the encapsulant.

Systems, devices, and methods for high die stack packages with secondary interposers are provided herein. A die stack package can include a first substrate, a first die stack carried by the first substrate, a second die stack carried by the first substrate, a second substrate carried by the first die stack and the second die stack, a third die stack carried by the second substrate, a fourth die stack carried by the second substrate, and one or more vertical wires electrically coupling the first substrate and the second substrate. Each of the first, second, third, and fourth die stacks can include a plurality of dies stacked in a cascading arrangement. In some embodiments, the first and second die stacks are each electrically coupled to the first substrate. In some embodiments, the first and second die stacks are each electrically coupled to the second substrate.