A semiconductor package includes a first substrate, a first semiconductor chip, a first bonding wire, a second substrate, a second semiconductor chip and a second bonding wire. The first substrate has a window through a center portion of the first substrate. The first semiconductor chip is located on the first substrate. The first bonding wire is in the window of the first substrate and electrically connects to the first semiconductor chip and the first substrate. The second substrate is located on the first semiconductor chip, and has a window through a center portion of the second substrate. The second substrate electrically connects to the first substrate. The second semiconductor chip is located on the second substrate. The second bonding wire is in the window of the second substrate and electrically connects to the second semiconductor chip and the second substrate.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

Provided is a semiconductor package including a package substrate having a first upper connection pad and a second upper connection pad provided on a top surface of the package substrate, a semiconductor chip disposed on the package substrate, a second semiconductor chip provided on the first semiconductor chip, a plurality of first chip pads and a plurality of second chip pads provided on top surfaces of the first semiconductor chip and the second semiconductor chip, respectively, a plurality of first conductive patterns, a plurality of second conductive patterns, and a cross conductive pattern of which both ends are connected to the first conductive pattern, wherein the cross conductive pattern is provided on a top surface of the first semiconductor chip and the second conductive pattern, and the cross conductive pattern crosses the second cross conductive pattern.

A semiconductor package includes: a semiconductor chip; a package substrate below the semiconductor chip in a vertical direction; and a plurality of connection pads on a lower surface of the package substrate, wherein the plurality of connection pads include: a first group of connection pads having a first width, and a second group of connection pads having a second width smaller than the first width, and wherein the first group of connection pads are provided closer to an edge boundary of a contact surface between the semiconductor chip and the package substrate than the second group of connection pads.

A semiconductor package includes a redistribution substrate, a chip stack structure disposed on the redistribution substrate and including a plurality of semiconductor chips disposed in a stack, a vertical wiring portion connecting the chip stack structure to the redistribution substrate and including a plurality of vertical wires that extend in a direction perpendicular to an upper surface of the redistribution substrate, a sealing member configured to seal at least a portion the chip stack structure and the vertical wiring portion, and a heat dissipation metal member disposed on side surfaces and an upper surface of the sealing member.

A semiconductor package includes a package substrate having an upper surface, a lower surface opposite to the upper surface, and a receiving groove that extends from the upper surface, toward the lower surface, by a predetermined depth; a first semiconductor chip in the receiving groove and protruding from the upper surface of the package substrate to have a predetermined height from the upper surface of the package substrate; an underfill member in the receiving groove and between the first semiconductor chip and an inner surface of the receiving groove; a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip; and a molding member on the package substrate and covering the first semiconductor chip and the plurality of second semiconductor chips.

A memory module may include a module substrate, a first memory package, a second memory package, and a module controller circuit. The module substrate may include first signal transmission lines and second signal transmission lines. Memory chips of the first memory package may be coupled in common to the first signal transmission lines. Memory chips of the second memory package may be coupled in common to the second signal transmission lines. The module controller circuit may connect a data bus to one of the first signal transmission lines and the second signal transmission lines based on a chip selection signal.

Provided is a printed circuit board including a substrate structure having a first surface including a chip mounting region on which a semiconductor chip is mounted and a second surface opposite to the first surface, the second surface having a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge and a first corner, a second corner, a third corner, and a fourth corner formed by the first to fourth edges, and pad patterns disposed on the second surface of the substrate structure, wherein the second surface includes a first region including a region corresponding to the chip mounting region and in contact with the first to fourth edges of the second surface, respectively, and second regions adjacent to the first to fourth corners of the second surface, respectively and spaced apart from each other by the first region, wherein the pad patterns include first pad patterns disposed in the first region and surface-treated with a nickel/gold (Ni/Au) layer, and second pad patterns disposed in the second regions and surface-treated with an organic solderability preservative.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.