A memory subsystem includes an I/O die, a host device, and a stacked memory structure. The I/O die includes a first surface and a second surface. The host device is stacked on the first surface of the I/O die to be at least partially bonded thereto. The stacked memory structure is stacked on the first surface of the I/O die to be at least partially bonded thereto. The I/O die includes a plurality of conductive pads arranged on the first surface. The stacked memory structure includes a plurality of memory dies stacked in a shingled manner so that a plurality of bonding pads is exposed, and a plurality of vertical wires respectively connecting the bonding pads of the plurality of memory dies to the plurality of conductive pads. The host device and the stacked memory structure is configured to interface with each other through the I/O die.

Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

A semiconductor package includes a memory die stack having a clock signal shared by lower and upper bytes. Each of a plurality of memory dies constituting the memory die stack of the semiconductor package includes a first clock circuit configured to generate a read clock signal for a lower byte and an upper byte constituting a data width of the memory die, and a plurality of first die bond pads corresponding to the number of ranks of a memory system including the memory die, and each of the plurality of first die bond pads is set for each rank. The first clock circuit is connected to, among the plurality of first die bond pads, a die bond pad corresponding to a rank to which the memory die belongs.

Systems and methods for measuring and predicting the strength of semiconductor devices and packaging are disclosed. In some embodiments, a semiconductor device assembly comprises a package substrate, a semiconductor die electrically coupled to the package substrate, and a molding covering at least a portion of the semiconductor die, where the molding includes a through-mold via (TMV) extending from an upper surface into the mold material to a depth. The semiconductor device assembly can include a strain gauge disposed in the molding at the depth of the TMV and be electrically coupled to the TMV. For example, the TMV can extend to the surface of the semiconductor die, to the package substrate, or other critical areas of the semiconductor device assembly, enabling strain to be measured at these depths. The semiconductor device assembly can be used in testing to predict the strength of the die and packaging in real-world scenarios, such as being dropped, bent, or crushed.

Implementations of an image sensor package may include an image sensor die including at least one bond pad thereon; a bond wire wirebonded to the at least one bond pad; and an optically transmissive lid coupled to the image sensor die with an optically opaque film adhesive over the at least one bond pad. The bond wire may extend through the optically opaque film adhesive to the at least one bond pad.

In this semiconductor device, an emitter electrode of a power semiconductor element includes a first sub-electrode provided in a region including a central portion of a front surface of a semiconductor substrate and a second sub-electrode provided in a region not including the central portion of the front surface of the semiconductor substrate. A first bonding wire connects the first sub-electrode and an emitter terminal. A second bonding wire connects the second sub-electrode and the emitter terminal. First and second voltage detectors detect voltages between the emitter terminal and the first and second sub-electrodes, respectively. It is possible to separately detect degradation of both the first bonding wire that degrades in an early period and the second bonding wire that degrades in a terminal period.

Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.

A method of forming a semiconductor package includes providing a semiconductor die that includes a bond pad disposed at an upper side of the semiconductor die, providing a carrier that includes a die attach pad and a landing pad, mounting the semiconductor die on the die attach pad with the bond pad facing away from the carrier, and attaching an electrical interconnect element between the bond pad and the landing pad, wherein the bond pad is formed from nanowires.

A power semiconductor device includes a plurality of power modules. Outer shapes of packages of the plurality of power modules are the same. The plurality of power modules include a first half-bridge module made of a first semiconductor, and at least one of a second half-bridge module made of a second semiconductor, a second relay module made of a second semiconductor, and a second diode module made of a second semiconductor.

A semiconductor device includes first and second transistors on a substrate of first conductivity type, and a well region between at least one of the first and second transistors and the substrate, and has second conductivity type different from first conductivity type. The first transistor includes a first channel layer on the substrate, a first barrier layer on the first channel layer, a first gate electrode on the first barrier layer, and a first source electrode and a first drain electrode on opposite sides of the first gate electrode, and connected to the first channel layer. The second transistor includes a second channel layer on the substrate, a second barrier layer on the second channel layer, a second gate electrode on the second barrier layer, and a second source electrode and a second drain electrode on opposite sides of the second gate electrode, and connected to the second channel layer.