A semiconductor package structure includes a substrate with a substrate surface, a processing device electrically coupled to the substrate surface, one or more radio frequency integrated circuits (RFIC(s)) electrically coupled to the substrate surface, and a shield plate. The shield plate is disposed between the one or more RFIC(s) and the processing device and is configured to couple the one or more RFIC(s) to a package ground via one or more conductors. The package ground has a ground voltage associated with the semiconductor package structure.

An electronic component is provided. The component includes: a base member, a Peltier element; a semiconductor element placed on a placement surface of the base member via the Peltier element; and a frame member arranged so as to surround a side surface of the semiconductor element. A first electrode provided in the semiconductor element is connected, via a conductive wire, to a second electrode provided in the frame member, and the base member and the frame member are bonded by a bonding member having a lower thermal conductivity than the base member.

Provided is a semiconductor package including a first redistribution structure, a second redistribution structure on the first redistribution structure, a first semiconductor device being between the first redistribution structure and the second redistribution structure, a first dummy chip being apart from the first semiconductor device in a lateral direction, a first connection wire being between the first semiconductor device and a first side surface of the first dummy chip, the first connection wire electrically connecting the first redistribution structure to the second redistribution structure, and a second connection wire being on a second side surface opposite to the first side surface of the first dummy chip, the second connection wire electrically connecting the first redistribution structure to the second redistribution structure.

A semiconductor device includes: a wiring board having a surface; a chip stack disposed above the surface and including a first semiconductor chip; a second semiconductor chip disposed between the surface and the chip stack; a spacer disposed between the surface and the first semiconductor chip, the spacer surrounding the second semiconductor chip along the surface, and the spacer containing a material higher in thermal conductivity than silicon; and a sealing insulation layer covering the chip stack.

A power chip packaging structure includes: a ceramic substrate; a first and a second top metal layers are formed on the ceramic substrate; a bottom metal layer formed on the ceramic substrate; a power chip having an active surface and a chip back surface. The active surface has a contact pad, and the chip back surface is connected to the first top metal layer. One or more first copper layers are formed on the contact pad, a top surface of the first copper layer has a peripheral region and an arrangement region surrounded by the peripheral region. Multiple second copper layers are formed in the arrangement region and separated from each other. Each of multiple wires is respectively connected to the second copper layer with one end and connected to the second top metal layer with the other end.

A power semiconductor device according to the present invention is provided with: a first circuit body constituting an upper arm of an inverter circuit for converting a DC current into an AC current; a second circuit body constituting a lower arm of the inverter circuit; and a circuit board that has therein a through-hole in which the first circuit body and the second circuit body are disposed and that has an intermediate board between the first circuit body and the second circuit body. The intermediate board has an AC wiring pattern for transmitting the AC current, and the first circuit body and the second circuit body are connected to the AC wiring pattern so as to be in surface contact with the AC wiring pattern.

A semiconductor device includes a plurality of semiconductor elements, each of which has a first electrode, a second electrode, and a third electrode, and is subjected to an ON-OFF control between the first electrode and the second electrode in accordance with a driving signal input to the third electrode. Further, the semiconductor device includes a control terminal to which the driving signal is input, a first wiring portion to which the control terminal is connected, a second wiring portion separated from the first wiring portion, a first connection member to conduct the first wiring portion and the second wiring portion, and a second connection member to conduct the second wiring portion and the third electrode of one of the plurality of semiconductor elements. The respective first electrodes of the plurality of semiconductor elements are electrically connected to one another, and respective second electrodes of the plurality of semiconductor elements are electrically connected to one another.

A semiconductor device includes a semiconductor die having a die surface, in which the die surface includes a bond pad. A ball bond has a distal surface and flattened-disk shape extending from the distal surface and terminating in a proximal surface spaced apart from the distal surface. The distal surface is coupled to the bond pad and a channel extends a depth into the proximal surface surrounding a central portion of the proximal surface. A bond wire extending from the central portion of the proximal surface, in which the channel is spaced apart from and surrounds the bond wire.

A semiconductor apparatus includes a substrate, a semiconductor device arranged on an upper surface of the substrate, a lead frame bonded to an upper surface of the semiconductor device via a bonding material, the lead frame having a first recess on an upper surface thereof, a wire connected to the first recess, and a resin that seals the substrate, the semiconductor device, the lead frame, and the wire.

A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.