A semiconductor package includes a package substrate having substrate pads disposed in a first direction on one surface, a semiconductor chip having chip pads disposed in the first direction, and bonding wires connecting the chip pads and the substrate pads. The bonding wires include first and second bonding wires alternately connected to the substrate pads respectively, in the first direction, the first bonding wires are connected to the substrate pads at a first angle less than a right angle with respect to a direction of the semiconductor chip, the second bonding wires are connected to the substrate pads at a second angle less than the first angle with respect to the direction of the semiconductor chip and a position at which the first bonding wires contact the substrate pads is closer to the semiconductor chip than a position at which the second bonding wires contact the substrate pads is to the semiconductor chip.

A semiconductor package includes a package substrate, a processor chip mounted on a first region of the package substrate, a plurality of memory chips mounted on a second region of the package substrate being spaced apart from the first region of the package substrate, a signal transmission device mounted on a third region of the package substrate between the first and second regions of the package substrate, and a plurality of first bonding wires connecting the plurality of memory chips to the signal transmission device. The signal transmission device includes upper pads connected to the plurality of first bonding wires, penetrating electrodes arranged in a main body portion of the signal transmission device and connected to the upper pads, and lower pads in a lower surface portion of the signal transmission device and connected to the penetrating electrodes and connected to the package substrate via bonding balls.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

In some embodiments, a semiconductor package includes a package substrate that includes a first surface, a second surface that is opposite to the first surface, first substrate pads disposed on the first surface in a first row, and second substrate pads disposed on the first surface in a second row. The semiconductor package further includes a first semiconductor chip that includes first chip pads, lower bonding wires configured to respectively couple the first chip pads and the first substrate pads, a second semiconductor chip that includes second chip pads, upper bonding wires configured to respectively couple the second chip pads and the second substrate pads, and an encapsulant disposed on the package substrate and covering the first semiconductor chip and the second semiconductor chip. The lower bonding wires are ball-bonded to the first chip pads and stich-bonded to the first substrate pads.

A semiconductor package includes a package substrate including first and second power P-pads and first and second signal P-pads, a lower layer chip including first and second power L-pads and first and second signal L-pads, an upper layer chip offset from the lower layer chip and including first and second power U-pads and first and second signal U-pads. The first power and signal P-pads are alternatingly stacked, the first power and signal L-pads are alternatingly stacked, and the first power and signal U-pads are alternatingly stacked. The second power and signal P-pads are alternatingly stacked, the second power and signal L-pads are alternatingly stacked, and the second power and signal U-pads are alternatingly stacked. Bonding wires connect the first and second power U-pads, the first and second power L-pads, the second power U-pads and P-pads, and the second signal U-pads and P-pads.

A method of forming an integrated circuit (IC) is provided. The method includes forming a seed layer of a first metal material over a circuit on a device side of a semiconductor die. The method also includes forming a multi-layer conductive contact on the seed layer. The multi-layer conductive contact has a width in a first dimension and includes a plurality of layers of different metal materials and a portion of the seed layer extends outwardly from a periphery of the multi-layer conductive contact. The method further includes forming a sacrificial layer of the first metal material over the multi-layer conductive contact. The method yet further includes etching to remove the seed layer and the sacrificial layer.

A recording element unit includes a first electrode pad, a second electrode pad, and a wire for electrically connecting the first electrode pad and the second electrode pad. The wire has a plurality of bending points at which the wire is bent in the direction of extension of the wire between a first connection point and a second connection point. The plurality of bending points include a first bending point at a height from the first connection point of at least 100 m and not more than 200 m, a second bending point at a distance from the first bending point in the horizontal direction of at least 100 m and not more than 270 m, and a third bending point at a distance from the intermediate point between the first electrode pad and the second electrode pad in the horizontal direction of within 150 m.

A bonding pad structure and a method of manufacturing a bonding pad structure are provided. The bonding pad structure includes a carrier, a first conductive layer disposed over the carrier, a second conductive layer disposed on the first conductive layer and contacting the first conductive layer, and a third conductive layer disposed on the second conductive layer and contacting the second conductive layer. The bonding pad structure also includes a first passivation layer disposed on the first conductive layer and contacting at least one of the first conductive layer or the second conductive layer. An upper surface of the third conductive layer facing away from the carrier is exposed from the first passivation layer.

A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.

An electronic device is provided. An example electronic device includes: a support structure including a substrate of dielectric material, a top conductive structure, arranged above the substrate, and a bottom conductive structure, arranged below the substrate, the top conductive structure including an annular region, the bottom conductive structure including an array of contacts; a cap coupled to the annular region such that the cap and the support structure delimit a cavity; and at least one semiconductive die in the cavity that generates one or more electric output signals. The array of contacts includes: signal contacts, which receive corresponding electric output signals or electric signals generated outside the electronic device; and reference contacts set to a reference potential. The electronic device further includes a plurality of reinforcement conductive vias, each extending through the substrate and has ends fixed respectively to the annular region and to a corresponding reference contact.